#!/usr/bin/env python3 # # This file is part of LiteX-Boards. # # Copyright (c) 2021 Shinken Sanada # SPDX-License-Identifier: BSD-2-Clause from migen import * from litex.gen import LiteXModule from litex_boards.platforms import ego1 from litex.soc.cores.clock import * from litex.soc.integration.soc import SoCRegion from litex.soc.integration.soc_core import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser from litex.soc.cores.video import VideoVGAPHY # CRG ---------------------------------------------------------------------------------------------- class _CRG(LiteXModule): def __init__(self, platform, sys_clk_freq): self.rst = Signal() self.cd_sys = ClockDomain() self.cd_vga = ClockDomain() self.pll = pll = S7PLL(speedgrade=-1) self.comb += pll.reset.eq(~platform.request("cpu_reset") | self.rst) pll.register_clkin(platform.request("clk100"), 100e6) pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_vga, 25e6) # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(100e6), with_led_chaser=True, with_video_terminal=False, **kwargs): platform = ego1.Platform() # CRG -------------------------------------------------------------------------------------- self.crg = _CRG(platform, sys_clk_freq) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on EGO1 Board", **kwargs) # VGA terminal ----------------------------------------------------------------------------- if with_video_terminal: self.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga") self.add_video_terminal(phy=self.videophy, timings="640x480@75Hz", clock_domain="vga") # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) # Build -------------------------------------------------------------------------------------------- def main(): from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=ego1.Platform, description="LiteX SoC on EGO1") parser.add_target_argument("--flash", action="store_true", help="Flash bitstream.") parser.add_target_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal.") parser.add_target_argument("--sys-clk-freq", default=100e6, help="System clock frequency.") args = parser.parse_args() soc = BaseSoC( sys_clk_freq = int(float(args.sys_clk_freq)), with_video_terminal = args.with_video_terminal, **parser.soc_argdict ) builder = Builder(soc, **parser.builder_argdict) if args.build: builder.build(**parser.toolchain_argdict) if args.load: prog = soc.platform.create_programmer() prog.load_bitstream(builder.get_bitstream_filename(mode="sram")) if args.flash: prog = soc.platform.create_programmer() prog.load_bitstream(builder.get_bitstream_filename(mode="flash")) if __name__ == "__main__": main()