#!/usr/bin/env python3 # # This file is part of LiteX-Boards. # # Copyright (c) 2022 Joseph FAYE # SPDX-License-Identifier: BSD-2-Clause from migen import * from litex.gen import * from litex_boards.platforms import xilinx_zcu102 from litex.build.io import CRG from litex.soc.integration.soc_core import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=125e6, with_ethernet=False, with_led_chaser=True, **kwargs): platform = xilinx_zcu102.Platform() # CRG -------------------------------------------------------------------------------------- self.crg = CRG(platform.request("clk125")) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on ZCU102", **kwargs) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq ) # Build -------------------------------------------------------------------------------------------- def main(): from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=xilinx_zcu102.Platform, description="LiteX SoC on ZCU102.") parser.add_target_argument("--sys-clk-freq", default=125e6, type=float, help="System clock generator.") args = parser.parse_args() soc = BaseSoC(sys_clk_freq=args.sys_clk_freq, **parser.soc_argdict) builder = Builder(soc, **parser.builder_argdict) if args.build: builder.build(**parser.toolchain_argdict) if args.load: prog = soc.platform.create_programmer() prog.load_bitstream(builder.get_bitstream_filename(mode="sram")) if __name__ == "__main__": main()