#!/usr/bin/env python3 # # This file is part of LiteX-Boards. # # Copyright (c) 2019-2020 Florent Kermarrec , # Copyright (c) 2021 Dhiru Kholia , # SPDX-License-Identifier: BSD-2-Clause from migen import * from litex.gen import LiteXModule from litex_boards.platforms import ebaz4205 from litex.soc.interconnect import axi from litex.soc.interconnect import wishbone from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser # CRG ---------------------------------------------------------------------------------------------- class _CRG(LiteXModule): def __init__(self, platform, sys_clk_freq, use_ps7_clk=False): self.rst = Signal() self.cd_sys = ClockDomain() # # # if use_ps7_clk: assert sys_clk_freq == 100e6 self.comb += ClockSignal("sys").eq(ClockSignal("ps7")) self.comb += ResetSignal("sys").eq(ResetSignal("ps7") | self.rst) else: self.pll = pll = S7PLL(speedgrade=-1) self.comb += pll.reset.eq(self.rst) pll.register_clkin(platform.request("clk33_333"), 33.333e6) pll.create_clkout(self.cd_sys, sys_clk_freq) # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(100e6), with_led_chaser=True, **kwargs): platform = ebaz4205.Platform() # CRG -------------------------------------------------------------------------------------- self.crg = _CRG(platform, sys_clk_freq) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on EBAZ4205", **kwargs) # Zynq7000 Integration --------------------------------------------------------------------- if kwargs.get("cpu_type", None) == "zynq7000": raise NotImplementedError # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) # Build -------------------------------------------------------------------------------------------- def main(): from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=ebaz4205.Platform, description="LiteX SoC on EBAZ4205") parser.add_target_argument("--sys-clk-freq", default=100e6, help="System clock frequency.") args = parser.parse_args() soc = BaseSoC( sys_clk_freq = int(float(args.sys_clk_freq)), **parser.soc_core_argdict ) builder = Builder(soc, **parser.builder_argdict) if args.build: builder.build(**parser.toolchain_argdict) if args.load: prog = soc.platform.create_programmer() prog.load_bitstream(builder.get_bitstream_filename(mode="sram"), device=1) if __name__ == "__main__": main()