#!/usr/bin/env python3 # This file is Copyright (c) 2020 Florent Kermarrec # License: BSD import os import argparse from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer from litex_boards.platforms import pano_logic_g2 from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * from litex.soc.integration.builder import * # CRG ---------------------------------------------------------------------------------------------- class _CRG(Module): def __init__(self, platform, clk_freq): self.clock_domains.cd_sys = ClockDomain() # # # self.submodules.pll = pll = S6PLL(speedgrade=-2) pll.register_clkin(platform.request("clk125"), 125e6) pll.create_clkout(self.cd_sys, clk_freq) # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(50e6), **kwargs): platform = pano_logic_g2.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # Build -------------------------------------------------------------------------------------------- def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Pano Logic G2") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) soc_core_args(parser) args = parser.parse_args() soc = BaseSoC(**soc_core_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) if args.load: prog = soc.platform.create_programmer() prog.load_bitstream(os.path.join(builder.gateware_dir, "top.sof")) if __name__ == "__main__": main()