141 lines
5.4 KiB
Python
141 lines
5.4 KiB
Python
from litex.build.generic_platform import *
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from litex.build.xilinx import Xilinx7SeriesPlatform
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from litex.build.openocd import OpenOCD
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk100", 0, Pins("C18"), IOStandard("LVCMOS33")),
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# Leds
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("user_led", 0, Pins("T20"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("U20"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("W20"), IOStandard("LVCMOS33")),
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# Serial
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("serial", 0,
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Subsignal("tx", Pins("R19")),
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Subsignal("rx", Pins("P19")),
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IOStandard("LVCMOS33"),
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),
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("serial", 1,
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Subsignal("tx", Pins("U21")),
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Subsignal("rx", Pins("T21")),
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IOStandard("LVCMOS33"),
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),
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# DDR3 SDRAM (voltage changed from 1.5V to 1.35V)
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("ddram", 0,
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Subsignal("a", Pins(
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"M2 M5 M3 M1 L6 P1 N3 N2",
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"M6 R1 L5 N5 N4 P2 P6"),
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IOStandard("SSTL135")),
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Subsignal("ba", Pins("L3 K6 L4"), IOStandard("SSTL135")),
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Subsignal("ras_n", Pins("J4"), IOStandard("SSTL135")),
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Subsignal("cas_n", Pins("K3"), IOStandard("SSTL135")),
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Subsignal("we_n", Pins("L1"), IOStandard("SSTL135")),
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Subsignal("dm", Pins("G3 F1"), IOStandard("SSTL135")),
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Subsignal("dq", Pins(
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"G2 H4 H5 J1 K1 H3 H2 J5",
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"E3 B2 F3 D2 C2 A1 E2 B1"),
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IOStandard("SSTL135"),
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Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("dqs_p", Pins("K2 E1"),
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IOStandard("DIFF_SSTL135"),
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Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("dqs_n", Pins("J2 D1"),
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IOStandard("DIFF_SSTL135"),
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Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("clk_p", Pins("P5"), IOStandard("DIFF_SSTL135")),
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Subsignal("clk_n", Pins("P4"), IOStandard("DIFF_SSTL135")),
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Subsignal("cke", Pins("J6"), IOStandard("SSTL135")),
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Subsignal("odt", Pins("K4"), IOStandard("SSTL135")),
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Subsignal("reset_n", Pins("G1"), IOStandard("SSTL135")),
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Misc("SLEW=FAST"),
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),
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# eMMC - there are pullups on the board so we don't enable them here
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("sdcard", 0,
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Subsignal("data", Pins("P17 W17 R18 V18")),
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Subsignal("cmd", Pins("Y19")),
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Subsignal("clk", Pins("Y18")),
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#Subsignal("cd", Pins(),
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Misc("SLEW=FAST"),
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IOStandard("LVCMOS33"),
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),
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# RGMII Ethernet
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("eth_ref_clk", 0, Pins("H19"), IOStandard("LVCMOS33")), # 125 MHz if enabled?
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("eth_clocks", 0,
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Subsignal("tx", Pins("J19")),
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Subsignal("rx", Pins("K19")),
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IOStandard("LVCMOS33")
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),
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("eth", 0,
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Subsignal("rst_n", Pins("N18"), IOStandard("LVCMOS33")),
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Subsignal("int_n", Pins("N20"), IOStandard("LVCMOS33")),
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Subsignal("mdio", Pins("M21"), IOStandard("LVCMOS33")),
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Subsignal("mdc", Pins("N22"), IOStandard("LVCMOS33")),
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Subsignal("rx_ctl", Pins("M22"), IOStandard("LVCMOS33")),
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Subsignal("rx_data", Pins("L20 L21 K21 K22"), IOStandard("LVCMOS33")),
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Subsignal("tx_ctl", Pins("J22"), IOStandard("LVCMOS33")),
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Subsignal("tx_data", Pins("G20 H20 H22 J21"), IOStandard("LVCMOS33")),
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),
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# PCIe
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("pcie_x1", 0,
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# Subsignal("rst_n", Pins(""), IOStandard("LVCMOS33")),
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Subsignal("clk_p", Pins("F6")),
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Subsignal("clk_n", Pins("E6")),
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Subsignal("rx_p", Pins("B8")),
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Subsignal("rx_n", Pins("A8")),
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Subsignal("tx_p", Pins("B4")),
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Subsignal("tx_n", Pins("A4"))
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),
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# USB ULPI
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("ulpi_clock", 0, Pins("W19"), IOStandard("LVCMOS33")),
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("ulpi", 0,
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Subsignal("data", Pins("AB18 AA18 AA19 AB20 AA20 AB21 AA21 AB22")),
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Subsignal("dir", Pins("W21")),
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Subsignal("stp", Pins("Y22")),
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Subsignal("nxt", Pins("W22")),
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Subsignal("rst", Pins("V20")),
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IOStandard("LVCMOS33"), Misc("SLEW=FAST")
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),
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("ulpi_clock", 1, Pins("V4"), IOStandard("LVCMOS33")),
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("ulpi", 1,
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Subsignal("data", Pins("AB2 AA3 AB3 Y4 AA4 AB5 AA5 AB6")),
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Subsignal("dir", Pins("AB7")),
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Subsignal("stp", Pins("AA6")),
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Subsignal("nxt", Pins("AB8")),
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Subsignal("rst", Pins("AA8")),
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IOStandard("LVCMOS33"), Misc("SLEW=FAST")
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(Xilinx7SeriesPlatform):
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default_clk_name = "clk100"
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default_clk_period = 1e9/100e6
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def __init__(self, device="xc7a100tfgg484-1", toolchain="vivado"):
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Xilinx7SeriesPlatform.__init__(self, device, _io, toolchain=toolchain)
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# self.toolchain.bitstream_commands = \
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# ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
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# self.toolchain.additional_commands = \
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# ["write_cfgmem -force -format bin -interface spix4 -size 16 "
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# "-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 35]")
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def create_programmer(self):
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bscan_spi = "bscan_spi_xc7a100t.bit" if "xc7a100t" in self.device else "bscan_spi_xc7a35t.bit"
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return OpenOCD("openocd_xc7_ft2232.cfg", bscan_spi)
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def do_finalize(self, fragment):
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Xilinx7SeriesPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
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