150 lines
5.6 KiB
Python
150 lines
5.6 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2024 Enjoy-Digital <enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.lattice import LatticeNexusPlatform
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from litex.build.openfpgaloader import OpenFPGALoader
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# 4. CertusPro-NX Clock Sources.
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("clk161_1", 0,
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Subsignal("p", Pins("C14"), IOStandard("LVDS")), # F_SFP_161.1328Mhz_CLK_P
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Subsignal("n", Pins("D13"), IOStandard("LVDS")), # F_SFP_161.1328Mhz_CLK_N
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),
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("clkin125", 0, Pins("P24"), IOStandard("LVCMOS33")), # F_CLKIN_125Mhz / BANK6
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("clk125", 0,
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Subsignal("p", Pins("W24"), IOStandard("LVDS")), # F_125Mhz_P
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Subsignal("n", Pins("W23"), IOStandard("LVDS")), # F_125Mhz_N
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),
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("clk100", 0,
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Subsignal("p", Pins("AB19"), IOStandard("LVDS")), # F_DDR_100Mhz_P
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Subsignal("n", Pins("AB18"), IOStandard("LVDS")), # F_DDR_100Mhz_N
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),
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# 7.2. General Purpose Push Buttons - all logic zero when pressed.
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("programn", 0, Pins("G4"), IOStandard("LVCMOS33")), # SW2
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("gsrn", 0, Pins("N9"), IOStandard("LVCMOS33")), # SW3
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("user_btn", 0, Pins("H21"), IOStandard("LVCMOS33")), # SW7
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# 7.1. DIP Switch.
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("user_dip_btn", 0, Pins("AA23"), IOStandard("LVCMOS33")),
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("user_dip_btn", 1, Pins("AB22"), IOStandard("LVCMOS33")),
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("user_dip_btn", 2, Pins("AC22"), IOStandard("LVCMOS33")),
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("user_dip_btn", 3, Pins("AA22"), IOStandard("LVCMOS33")),
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("user_dip_btn", 4, Pins("W21"), IOStandard("LVCMOS33")),
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# 6.2 UART Topology (FTDI with J32&J33).
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("serial", 0,
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Subsignal("rx", Pins("L8"), IOStandard("LVCMOS33")),
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Subsignal("tx", Pins("M9"), IOStandard("LVCMOS33")),
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),
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# 7.3. General Purpose LEDs (Inverted).
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("user_led", 0, Pins("R5"), IOStandard("LVCMOS33")), # Bank 1 Green
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("user_led", 1, Pins("R4"), IOStandard("LVCMOS33")), # Bank 1 Green
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("user_led", 2, Pins("R8"), IOStandard("LVCMOS33")), # Bank 1 Green
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("user_led", 3, Pins("R9"), IOStandard("LVCMOS33")), # Bank 1 Green
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("user_led", 4, Pins("U8"), IOStandard("LVCMOS33")), # Bank 1 Green
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("user_led", 5, Pins("R7"), IOStandard("LVCMOS33")), # Bank 1 Green
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("user_led", 6, Pins("R6"), IOStandard("LVCMOS33")), # Bank 1 Green
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("user_led", 7, Pins("P8"), IOStandard("LVCMOS33")), # Bank 1 Green
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# 6.1. I2C Topology (FTDI with J32&J33).
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("i2c", 0,
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Subsignal("scl", Pins("M7")),
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Subsignal("sda", Pins("M6")),
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),
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# 6.3. SPI Topology.
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("spiflash", 0,
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Subsignal("cs_n", Pins("H3")),
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Subsignal("clk", Pins("G6")),
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Subsignal("mosi", Pins("H7")),
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Subsignal("miso", Pins("H6")),
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Subsignal("wp", Pins("K5")),
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Subsignal("hold", Pins("H4")),
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IOStandard("LVCMOS33")
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),
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("spiflash4x", 0,
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Subsignal("cs_n", Pins("H3")),
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Subsignal("clk", Pins("G6")),
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Subsignal("dq", Pins("H7 H6 K5 H4")),
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IOStandard("LVCMOS33")
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),
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# 8.1 SMA Connectors.
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("sma_tx", 0,
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Subsignal("p", Pins("A18")), # J6
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Subsignal("n", Pins("A17")), # J3
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),
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("sma_tx", 1,
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Subsignal("p", Pins("A15")), # J11
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Subsignal("n", Pins("A14")), # J9
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),
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("sma_rx", 0,
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Subsignal("p", Pins("C16")), # J8
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Subsignal("n", Pins("B16")), # J10
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),
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("sma_rx", 1,
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Subsignal("p", Pins("B20")), # J2
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Subsignal("n", Pins("B19")), # J5
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),
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# 8.8 PCIe Edge Connector.
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("pcie_x4", 0,
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Subsignal("clk_p", Pins("F20")), # 100MHz ref clk.
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Subsignal("clk_n", Pins("E20")),
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Subsignal("rx_p", Pins("G24 E24 C24 C21")),
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Subsignal("rx_n", Pins("G25 D25 B23 C22")),
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Subsignal("tx_p", Pins("F26 C26 A25 A22")),
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Subsignal("tx_n", Pins("E26 B26 A24 A21")),
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Subsignal("perst", Pins("R26"), IOStandard("LVCMOS33")),
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Subsignal("refret", Pins("E22 G21 E19 D18")), # serdes analog reference return for PMA PLL
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Subsignal("rext", Pins("E21 G20 D19 C18")), # serdes external resistor for calibration
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),
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("pcie_ctrl", 0,
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Subsignal("sw_sel", Pins("AF25")),
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Subsignal("clk_sel", Pins("AB25")),
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Subsignal("sw1_pd", Pins("T6")),
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Subsignal("sw2_pd", Pins("T5")),
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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# 8.5 PMOD Header
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# PMOD signal number:
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# 1 2 3 4 7 8 9 10
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("PMOD0", "T3 T2 U1 U6 V2 W1 W3 AB1"), # J64
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("PMOD1", "T1 U2 U3 V1 V3 W2 Y1 AA1"), # J65
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(LatticeNexusPlatform):
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default_clk_name = "clkin125"
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default_clk_period = 1e9/125e6
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def __init__(self, device="LFCPNX", toolchain="radiant", **kwargs):
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assert device in ["LFCPNX"]
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LatticeNexusPlatform.__init__(self, device + "-100-9LFG672I", _io, _connectors, toolchain=toolchain, **kwargs)
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# SPI Pins may be used as General IO Pins (see FPGA-AN-02048 4.1.7)
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self.add_platform_command("ldc_set_sysconfig {{MASTER_SPI_PORT=DISABLE}}")
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# Evaluation mode (with free license)
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self.toolchain.set_prj_strategy_opts({"bit_ip_eval": "true"})
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def create_programmer(self):
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return OpenFPGALoader()
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def do_finalize(self, fragment):
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LatticeNexusPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clkin125", loose=True), 1e9/125e6)
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