106 lines
3.8 KiB
Python
106 lines
3.8 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2016-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.lattice import LatticePlatform
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from litex.build.lattice.programmer import LatticeProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk12", 0, Pins("C8"), IOStandard("LVCMOS33")),
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("rst_n", 0, Pins("B3"), IOStandard("LVCMOS33")),
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# Leds
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("user_led", 0, Pins("H11"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("J13"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("J11"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("L12"), IOStandard("LVCMOS33")),
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("user_led", 4, Pins("K11"), IOStandard("LVCMOS33")),
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("user_led", 5, Pins("L13"), IOStandard("LVCMOS33")),
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("user_led", 6, Pins("N15"), IOStandard("LVCMOS33")),
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("user_led", 7, Pins("P16"), IOStandard("LVCMOS33")),
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# Switches
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("user_dip_btn", 0, Pins("N2"), IOStandard("LVCMOS33")),
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("user_dip_btn", 1, Pins("P1"), IOStandard("LVCMOS33")),
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("user_dip_btn", 2, Pins("M3"), IOStandard("LVCMOS33")),
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("user_dip_btn", 3, Pins("N1"), IOStandard("LVCMOS33")),
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# Serial
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("serial", 0,
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Subsignal("tx", Pins("C11"), IOStandard("LVCMOS33")),
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Subsignal("rx", Pins("A11"), IOStandard("LVCMOS33")),
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(LatticePlatform):
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default_clk_name = "clk12"
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default_clk_period = 1e9/12e6
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def __init__(self, toolchain="diamond"):
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LatticePlatform.__init__(self, "LCMXO3L-6900C-5BG256C", _io, toolchain=toolchain)
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def create_programmer(self):
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_xcf_template = """
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<?xml version='1.0' encoding='utf-8' ?>
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<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
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<ispXCF version="3.6.0">
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<Comment></Comment>
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<Chain>
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<Comm>JTAG</Comm>
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<Device>
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<SelectedProg value="TRUE"/>
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<Pos>1</Pos>
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<Vendor>Lattice</Vendor>
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<Family>MachXO3L</Family>
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<Name>LCMXO3L-6900C</Name>
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<IDCode>0x412bd043</IDCode>
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<Package>All</Package>
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<PON>LCMXO3L-6900C</PON>
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<Bypass>
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<InstrLen>8</InstrLen>
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<InstrVal>11111111</InstrVal>
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<BScanLen>1</BScanLen>
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<BScanVal>0</BScanVal>
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</Bypass>
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<File>{bitstream_file}</File>
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<JedecChecksum>N/A</JedecChecksum>
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<Operation>SRAM Fast Configuration</Operation>
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<Option>
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<SVFVendor>JTAG STANDARD</SVFVendor>
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<IOState>HighZ</IOState>
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<PreloadLength>664</PreloadLength>
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<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
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<Usercode>0x00000000</Usercode>
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<AccessMode>SRAM</AccessMode>
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</Option>
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</Device>
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</Chain>
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<ProjectOptions>
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<Program>SEQUENTIAL</Program>
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<Process>ENTIRED CHAIN</Process>
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<OperationOverride>No Override</OperationOverride>
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<StartTAP>TLR</StartTAP>
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<EndTAP>TLR</EndTAP>
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<VerifyUsercode value="FALSE"/>
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</ProjectOptions>
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<CableOptions>
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<CableName>USB2</CableName>
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<PortAdd>FTUSB-0</PortAdd>
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<USBID>Lattice XO3L Starter Kit A Location 0000 Serial A</USBID>
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</CableOptions>
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</ispXCF>
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"""
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return LatticeProgrammer(_xcf_template)
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def do_finalize(self, fragment):
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LatticePlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk12", loose=True), 1e9/12e6)
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