107 lines
4.2 KiB
Python
107 lines
4.2 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020 Krzysztof Jankowski <yanekx@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.altera import AlteraPlatform
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from litex.build.altera.programmer import USBBlaster
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk27", 0, Pins("54")),
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("clk27", 0, Pins("54")),
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# Leds
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("user_led", 0, Pins("7"),
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Misc("CURRENT_STRENGTH_NEW 4MA")),
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# Serial
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("serial", 0,
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Subsignal("tx", Pins("46")),
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Subsignal("rx", Pins("31")),
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),
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# VGA
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("vga", 0,
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Subsignal("hsync_n", Pins("119")),
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Subsignal("vsync_n", Pins("136")),
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Subsignal("r", Pins("135 137 141 142 143 144")),
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Subsignal("g", Pins("106 110 111 112 113 114")),
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Subsignal("b", Pins("115 120 121 125 132 133")),
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Misc("CURRENT_STRENGTH_NEW \"MAXIMUM CURRENT\""),
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),
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# Audio
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("audio", 0,
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Subsignal("l", Pins("65")),
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Subsignal("r", Pins("80")),
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Misc("CURRENT_STRENGTH_NEW 4MA"),
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),
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# SPI
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("spi", 0,
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Subsignal("do", Pins("105")),
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Subsignal("di", Pins("88")),
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Subsignal("sck", Pins("126")),
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Subsignal("ss2", Pins("127")),
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Subsignal("ss3", Pins("91")),
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Subsignal("ss4", Pins("90")),
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),
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# SDR SDRAM
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("sdram_clock", 0, Pins("43"),
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Misc("CURRENT_STRENGTH_NEW \"MAXIMUM CURRENT\""), IOStandard("3.3-V LVTTL")),
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("sdram", 0,
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Subsignal("a", Pins("49 44 42 39 4 6 8 10 11 28 50 30 32")),
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Subsignal("dq", Pins("83 79 77 76 72 71 69 68 86 87 98 99 100 101 103 104"),
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Misc("FAST_INPUT_REGISTER ON"), Misc("FAST_OUTPUT_ENABLE_REGISTER ON")),
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Subsignal("ba", Pins("58 51")),
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Subsignal("dm", Pins("67 85")), # DQML, DQMH
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Subsignal("ras_n", Pins("60")),
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Subsignal("cas_n", Pins("64")),
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Subsignal("we_n", Pins("66")),
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Subsignal("cs_n", Pins("59")),
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Subsignal("cke", Pins("33")),
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Misc("FAST_OUTPUT_REGISTER ON"),
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Misc("CURRENT_STRENGTH_NEW \"MAXIMUM CURRENT\""),
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),
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# Others
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("conf_data0", 0, Pins("13")),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(AlteraPlatform):
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default_clk_name = "clk27"
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default_clk_period = 1e9/27e6
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def __init__(self, toolchain="quartus"):
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AlteraPlatform.__init__(self, "EP3C25E144C8", _io, toolchain="quartus")
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self.add_platform_command("set_global_assignment -name FAMILY \"Cyclone III\"")
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self.add_platform_command("set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144")
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self.add_platform_command("set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED")
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self.add_platform_command("set_global_assignment -name USE_CONFIGURATION_DEVICE OFF")
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self.add_platform_command("set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME \"PASSIVE SERIAL\"")
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self.add_platform_command("set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP \"AS INPUT TRI-STATED\"")
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self.add_platform_command("set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION \"USE AS REGULAR IO\"")
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self.add_platform_command("set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION \"USE AS REGULAR IO\"")
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self.add_platform_command("set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION \"USE AS REGULAR IO\"")
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self.add_platform_command("set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION \"USE AS REGULAR IO\"")
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self.add_platform_command("set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION \"USE AS REGULAR IO\"")
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self.add_platform_command("set_global_assignment -name STRATIX_DEVICE_IO_STANDARD \"3.3-V LVTTL\"")
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def create_programmer(self):
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return USBBlaster()
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def do_finalize(self, fragment):
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AlteraPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk27", 0, loose=True), 1e9/27e6)
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self.add_period_constraint(self.lookup_request("clk27", 1, loose=True), 1e9/27e6)
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