181 lines
6.4 KiB
Python
181 lines
6.4 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Hans Baier <hansfbaier@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc
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from litex.build.xilinx import Xilinx7SeriesPlatform
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from litex.build.openocd import OpenOCD
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk50", 0, Pins("N11"), IOStandard("LVCMOS33")),
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# The core board does not have a USB serial on it,
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# so you will have to attach an USB to serial adapter
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# on these pins
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("gpio_serial", 0,
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Subsignal("tx", Pins("J2:7")),
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Subsignal("rx", Pins("J2:8")),
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IOStandard("LVCMOS33")
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),
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# SPIFlash
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# MT25QL128
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("spiflash4x", 0, # clock needs to be accessed through STARTUPE2
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Subsignal("cs_n", Pins("L12")),
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Subsignal("clk", Pins("E8")),
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Subsignal("dq", Pins("J13", "J14", "K15", "K16")),
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IOStandard("LVCMOS33")
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),
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# DDR3 SDRAM
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# MT41J128M16JT-125K
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("ddram", 0,
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Subsignal("a", Pins("B14 C8 A14 C14 C9 B10 D9 A12 D8 A13 B12 A9 A8 B11"),
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IOStandard("SSTL135")),
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Subsignal("ba", Pins("C16 A15 B15"), IOStandard("SSTL135")),
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Subsignal("ras_n", Pins("B16"), IOStandard("SSTL135")),
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Subsignal("cas_n", Pins("C11"), IOStandard("SSTL135")),
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Subsignal("we_n", Pins("C12"), IOStandard("SSTL135")),
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# cs_n is hardwired on the board
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#Subsignal("cs_n", Pins("-"), IOStandard("SSTL135")),
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Subsignal("dm", Pins("F12 H11"), IOStandard("SSTL135")),
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Subsignal("dq", Pins(
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"F15 F13 E16 D11 E12 E13 D16 E11",
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"G12 J16 G16 J15 H14 H12 H16 H13"),
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IOStandard("SSTL135"),
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Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("dqs_p", Pins("D14 G14"),
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IOStandard("DIFF_SSTL135"),
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Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("dqs_n", Pins("D15 F14"),
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IOStandard("DIFF_SSTL135"),
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Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("clk_p", Pins("B9"), IOStandard("DIFF_SSTL135")),
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Subsignal("clk_n", Pins("A10"), IOStandard("DIFF_SSTL135")),
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Subsignal("cke", Pins("D13"), IOStandard("SSTL135")),
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Subsignal("odt", Pins("C13"), IOStandard("SSTL135")),
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Subsignal("reset_n", Pins("E15"), IOStandard("SSTL135")),
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Misc("SLEW=FAST"),
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),
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]
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# The connectors are named after the daughterboard, not the core board
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# because on the different core boards the names vary, but on the
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# daughterboard they stay the same, which we need to connect the
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# daughterboard peripherals to the core board.
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# On this board J2 is U7 and J3 is U8
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_connectors = [
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("J2", {
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# odd row even row
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7: "M12", 8: "N13",
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9: "N14", 10: "N16",
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11: "P15", 12: "P16",
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13: "R15", 14: "R16",
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15: "T14", 16: "T15",
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17: "P13", 18: "P14",
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19: "T13", 20: "R13",
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21: "T12", 22: "R12",
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23: "L13", 24: "N12",
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25: "K12", 26: "K13",
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27: "P10", 28: "P11",
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29: "N9", 30: "P9",
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31: "T10", 32: "R11",
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33: "T9", 34: "R10",
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35: "T8", 36: "R8",
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37: "T7", 38: "R7",
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39: "T5", 40: "R6",
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41: "P6", 42: "R5",
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43: "N6", 44: "M6",
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45: "L5", 46: "P5",
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47: "T4", 48: "T3",
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49: "R3", 50: "T2",
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51: "R2", 52: "R1",
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53: "M5", 54: "N4",
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55: "P4", 56: "P3",
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57: "N1", 58: "P1",
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59: "M2", 60: "M1",
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}),
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("J3", {
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# odd row even row
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7: "B7", 8: "A7",
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9: "B6", 10: "B5",
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11: "E6", 12: "K5",
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13: "J5", 14: "J4",
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15: "G5", 16: "G4",
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17: "C7", 18: "C6",
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19: "D6", 20: "D5",
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21: "A5", 22: "A4",
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23: "B4", 24: "A3",
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25: "D4", 26: "C4",
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27: "C3", 28: "C2",
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29: "B2", 30: "A2",
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31: "C1", 32: "B1",
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33: "E2", 34: "D1",
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35: "E3", 36: "D3",
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37: "F5", 38: "E5",
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39: "F2", 40: "E1",
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41: "F4", 42: "F3",
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43: "G2", 44: "G1",
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45: "H2", 46: "H1",
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47: "K1", 48: "J1",
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49: "L3", 50: "L2",
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51: "H5", 52: "H4",
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53: "J3", 54: "H3",
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55: "K3", 56: "K2",
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57: "L4", 58: "M4",
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59: "N3", 60: "N2",
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})
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(Xilinx7SeriesPlatform):
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default_clk_name = "clk50"
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default_clk_period = 1e9/50e6
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# these resources conflict with daughterboard resources
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# so they are only used if the daughterboard is not present
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core_resources = [
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("user_led", 0, Pins("E6"), IOStandard("LVCMOS33")),
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("cpu_reset", 0, Pins("K5"), IOStandard("LVCMOS33")),
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]
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def __init__(self, toolchain="vivado", with_daughterboard=False, with_core_resources=True):
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device = "xc7a35tftg256-1"
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io = _io
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connectors = _connectors
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if with_daughterboard:
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from litex_boards.platforms.qmtech_daughterboard import QMTechDaughterboard
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daughterboard = QMTechDaughterboard(IOStandard("LVCMOS33"))
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io += daughterboard.io
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connectors += daughterboard.connectors
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elif with_core_resources:
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io += self.core_resources
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Xilinx7SeriesPlatform.__init__(self, device, io, connectors, toolchain=toolchain)
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self.toolchain.bitstream_commands = \
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["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
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self.toolchain.additional_commands = \
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["write_cfgmem -force -format bin -interface spix4 -size 16 "
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"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 15]")
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self.add_platform_command("set_property CFGBVS VCCO [current_design]")
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self.add_platform_command("set_property CONFIG_VOLTAGE 3.3 [current_design]")
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def create_programmer(self):
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bscan_spi = "bscan_spi_xc7a35t.bit"
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return OpenOCD("openocd_xc7_ft2232.cfg", bscan_spi)
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def do_finalize(self, fragment):
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Xilinx7SeriesPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
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