124 lines
5.3 KiB
Python
124 lines
5.3 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020 Antmicro <www.antmicro.com>
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# Copyright (c) 2019 David Shah <dave@ds0.me>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxUSPPlatform, VivadoProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk125", 0,
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Subsignal("p", Pins("F23"), IOStandard("LVDS")),
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Subsignal("n", Pins("E23"), IOStandard("LVDS")),
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),
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("clk300", 0,
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Subsignal("p", Pins("AH18"), IOStandard("DIFF_SSTL12_DCI")),
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Subsignal("n", Pins("AH17"), IOStandard("DIFF_SSTL12_DCI")),
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),
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("cpu_reset", 0, Pins("M11"), IOStandard("LVCMOS33")),
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# Leds
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("user_led", 0, Pins("D5"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("D6"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("A5"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("B5"), IOStandard("LVCMOS33")),
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# Buttons
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("user_btn", 0, Pins("B4"), IOStandard("LVCMOS33")),
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("user_btn", 1, Pins("C4"), IOStandard("LVCMOS33")),
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("user_btn", 2, Pins("B3"), IOStandard("LVCMOS33")),
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("user_btn", 3, Pins("C3"), IOStandard("LVCMOS33")),
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# Switches
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("user_dip", 0, Pins("E4"), IOStandard("LVCMOS33")),
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("user_dip", 1, Pins("D4"), IOStandard("LVCMOS33")),
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("user_dip", 2, Pins("F5"), IOStandard("LVCMOS33")),
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("user_dip", 3, Pins("F4"), IOStandard("LVCMOS33")),
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# Serial
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("serial", 0,
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Subsignal("cts", Pins("A19")),
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Subsignal("rts", Pins("C18")),
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Subsignal("tx", Pins("C19")),
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Subsignal("rx", Pins("A20")),
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IOStandard("LVCMOS18")
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),
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# I2C
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("i2c", 0,
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Subsignal("sda", Pins("P12")),
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Subsignal("scl", Pins("N12")),
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IOStandard("LVCMOS33")
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),
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# DDR4 SDRAM
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("ddram", 0,
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Subsignal("a", Pins(
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"AH16 AG14 AG15 AF15 AF16 AJ14 AH14 AF17",
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"AK17 AJ17 AK14 AK15 AL18 AK18"),
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IOStandard("SSTL12_DCI")),
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Subsignal("ba", Pins("AL15 AL16"), IOStandard("SSTL12_DCI")),
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Subsignal("bg", Pins("AC16 AB16"), IOStandard("SSTL12_DCI")),
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Subsignal("ras_n", Pins("AD15"), IOStandard("SSTL12_DCI")), # A16
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Subsignal("cas_n", Pins("AA14"), IOStandard("SSTL12_DCI")), # A15
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Subsignal("we_n", Pins("AA16"), IOStandard("SSTL12_DCI")), # A14
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Subsignal("cs_n", Pins("AA15"), IOStandard("SSTL12_DCI")), # also AL17 AN17 AN16 for larger SODIMMs
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Subsignal("act_n", Pins("AC17"), IOStandard("SSTL12_DCI")),
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#Subsignal("alert_n", Pins("AB15"), IOStandard("SSTL12_DCI")),
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#Subsignal("par", Pins("AD16"), IOStandard("SSTL12_DCI")),
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Subsignal("dm", Pins("AH22 AE18 AL20 AP19 AF11 AH12 AK13 AN12"),
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IOStandard("POD12_DCI")),
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Subsignal("dq", Pins(
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"AE24 AE23 AF22 AF21 AG20 AG19 AH21 AG21",
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"AA20 AA19 AD19 AC18 AE20 AD20 AC19 AB19",
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"AJ22 AJ21 AK20 AJ20 AK19 AJ19 AL23 AL22",
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"AN23 AM23 AP23 AN22 AP22 AP21 AN19 AM19",
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"AC13 AB13 AF12 AE12 AF13 AE13 AE14 AD14",
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"AG8 AF8 AG10 AG11 AH13 AG13 AJ11 AH11",
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"AK9 AJ9 AK10 AJ10 AL12 AK12 AL10 AL11",
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"AM8 AM9 AM10 AM11 AP11 AN11 AP9 AP10"),
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IOStandard("POD12_DCI"),
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Misc("PRE_EMPHASIS=RDRV_240"),
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Misc("EQUALIZATION=EQ_LEVEL2")),
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Subsignal("dqs_p", Pins("AF23 AA18 AK22 AM21 AC12 AG9 AK8 AN9"),
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IOStandard("DIFF_POD12_DCI"),
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Misc("PRE_EMPHASIS=RDRV_240"),
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Misc("EQUALIZATION=EQ_LEVEL2")),
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Subsignal("dqs_n", Pins("AG23 AB18 AK23 AN21 AD12 AH9 AL8 AN8"),
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IOStandard("DIFF_POD12_DCI"),
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Misc("PRE_EMPHASIS=RDRV_240"),
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Misc("EQUALIZATION=EQ_LEVEL2")),
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Subsignal("clk_p", Pins("AF18"), IOStandard("DIFF_SSTL12_DCI")), # also AJ16 for larger SODIMMs
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Subsignal("clk_n", Pins("AG18"), IOStandard("DIFF_SSTL12_DCI")), # also AJ15 for larger SODIMMs
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Subsignal("cke", Pins("AD17"), IOStandard("SSTL12_DCI")), # also AM15 for larger SODIMMs
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Subsignal("odt", Pins("AE15"), IOStandard("SSTL12_DCI")), # also AM16 for larger SODIMMs
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Subsignal("reset_n", Pins("AB14"), IOStandard("LVCMOS12")),
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Misc("SLEW=FAST"),
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxUSPPlatform):
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default_clk_name = "clk125"
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default_clk_period = 1e9/125e6
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def __init__(self, toolchain="vivado"):
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XilinxUSPPlatform.__init__(self, "xczu7ev-ffvc1156-2-i", _io, toolchain=toolchain)
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def create_programmer(self):
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return VivadoProgrammer()
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def do_finalize(self, fragment):
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XilinxUSPPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk125", loose=True), 1e9/125e6)
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self.add_period_constraint(self.lookup_request("clk300", loose=True), 1e9/125e6)
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self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 64]")
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self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 65]")
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self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 66]")
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