122 lines
4.9 KiB
Python
Executable File
122 lines
4.9 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Andrew Dennison <andrew@motec.com.au>
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# Copyright (c) 2021 Franck Jullien <franck.jullien@collshade.fr>
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# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2022 Charles-Henri Mousset <ch.mousset@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.gen import *
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from litex.gen.genlib.misc import WaitTimer
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from litex_boards.platforms import efinix_t8f81_dev_kit
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_rst = ClockDomain(reset_less=True)
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# # #
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clk33 = platform.request("clk33")
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rst_n = platform.request("user_btn", 0)
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self.comb += self.cd_rst.clk.eq(clk33)
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# A pulse is necessary to do a reset.
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self.rst_pulse = Signal()
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self.reset_timer = reset_timer = ClockDomainsRenamer("rst")(WaitTimer(25e-6*platform.default_clk_freq))
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self.comb += self.rst_pulse.eq(self.rst ^ reset_timer.done)
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self.comb += reset_timer.wait.eq(self.rst)
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# PLL.
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self.pll = pll = TRIONPLL(platform)
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self.comb += pll.reset.eq(~rst_n | self.rst_pulse)
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pll.register_clkin(clk33, platform.default_clk_freq)
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pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=True)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, bios_flash_offset, sys_clk_freq=33.333e6, with_led_chaser=True, **kwargs):
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platform = efinix_t8f81_dev_kit.Platform()
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# CRG --------------------------------------------------------------------------------------
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self.crg = _CRG(platform, sys_clk_freq)
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# SoCCore ----------------------------------------------------------------------------------
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# Disable Integrated ROM.
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kwargs["integrated_rom_size"] = 0
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# Set CPU variant / reset address
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if kwargs.get("cpu_type", "vexriscv") == "vexriscv":
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kwargs["cpu_variant"] = "minimal"
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Efinix T8F81 Dev Kit", **kwargs)
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# SPI Flash --------------------------------------------------------------------------------
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from litespi.modules import W25Q80BV
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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self.add_spi_flash(mode="1x", module=W25Q80BV(Codes.READ_1_1_1), with_master=False)
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# Add ROM linker region --------------------------------------------------------------------
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self.bus.add_region("rom", SoCRegion(
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origin = self.bus.regions["spiflash"].origin + bios_flash_offset,
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size = 32 * KILOBYTE,
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linker = True)
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)
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self.cpu.set_reset_address(self.bus.regions["rom"].origin)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=efinix_t8f81_dev_kit.Platform, description="LiteX SoC on Efinix T8F81C Dev Kit.")
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parser.add_target_argument("--flash", action="store_true", help="Flash Bitstream.")
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parser.add_target_argument("--sys-clk-freq", default=33.333e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--bios-flash-offset", default="0x40000", help="BIOS offset in SPI Flash.")
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args = parser.parse_args()
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soc = BaseSoC(
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bios_flash_offset = int(args.bios_flash_offset, 0),
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sys_clk_freq = args.sys_clk_freq,
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**parser.soc_argdict)
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.add_hex(0, builder.get_bitstream_filename(mode="sram"))
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prog.load()
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if args.flash:
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prog = soc.platform.create_programmer()
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prog.add_hex(0, builder.get_bitstream_filename(mode="sram"))
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prog.add_bin(int(args.bios_flash_offset, 0), builder.get_bios_filename())
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prog.flash()
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if __name__ == "__main__":
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main()
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