146 lines
5.7 KiB
Python
Executable File
146 lines
5.7 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2019 Sean Cross <sean@xobs.io>
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# Copyright (c) 2018 David Shah <dave@ds0.me>
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# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.gen import *
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from litex_boards.platforms import lattice_ice40up5k_evn
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from litex.build.lattice.programmer import IceStormProgrammer
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from litex.soc.cores.ram import Up5kSPRAM
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from litex.soc.cores.clock import iCE40PLL
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq):
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assert sys_clk_freq == 12e6
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_por = ClockDomain()
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# # #
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# Clk/Rst
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sys = platform.request("clk12")
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platform.add_period_constraint(sys, 1e9/12e6)
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# Power On Reset
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por_count = Signal(16, reset=2**16-1)
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por_done = Signal()
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self.comb += self.cd_por.clk.eq(ClockSignal("sys"))
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self.comb += por_done.eq(por_count == 0)
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self.sync.por += If(~por_done, por_count.eq(por_count - 1))
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# Sys Clk
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self.comb += self.cd_sys.clk.eq(sys)
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self.specials += AsyncResetSynchronizer(self.cd_sys, ~por_done)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, bios_flash_offset, sys_clk_freq=12e6,
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with_led_chaser = True,
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**kwargs):
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platform = lattice_ice40up5k_evn.Platform()
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# CRG --------------------------------------------------------------------------------------
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self.crg = _CRG(platform, sys_clk_freq)
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# SoCCore ----------------------------------------------------------------------------------
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# Disable Integrated ROM/SRAM since too large for iCE40 and UP5K has specific SPRAM.
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kwargs["integrated_sram_size"] = 0
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kwargs["integrated_rom_size"] = 0
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Lattice iCE40UP5k EVN breakout board", **kwargs)
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# 128KB SPRAM (used as SRAM) ---------------------------------------------------------------
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self.spram = Up5kSPRAM(size=128 * KILOBYTE)
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self.bus.add_slave("sram", self.spram.bus, SoCRegion(origin=self.mem_map["sram"], size=128 * KILOBYTE))
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# SPI Flash --------------------------------------------------------------------------------
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# 4x mode is not possible on this board since WP and HOLD pins are not connected to the FPGA
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from litespi.modules import N25Q032A
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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self.add_spi_flash(mode="1x", module=N25Q032A(Codes.READ_1_1_1))
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# Add ROM linker region --------------------------------------------------------------------
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self.bus.add_region("rom", SoCRegion(
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origin = self.bus.regions["spiflash"].origin + bios_flash_offset,
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size = 32 * KILOBYTE,
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linker = True)
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)
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self.cpu.set_reset_address(self.bus.regions["rom"].origin)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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pads = platform.request_all("user_led_n"),
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sys_clk_freq = sys_clk_freq)
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# Flash --------------------------------------------------------------------------------------------
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def flash(bios_flash_offset, target="lattice_ice40up5k_evn"):
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from litex.build.dfu import DFUProg
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prog = IceStormProgrammer()
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bitstream = open("build/"+target+"/gateware/"+target+".bin", "rb")
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bios = open("build/"+target+"/software/bios/bios.bin", "rb")
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image = open("build/"+target+"/image.bin", "wb")
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# Copy bitstream at 0x00000000
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for i in range(0x00000000, 0x0020000):
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b = bitstream.read(1)
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if not b:
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image.write(0xff.to_bytes(1, "big"))
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else:
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image.write(b)
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# Copy bios at 0x00020000
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for i in range(0x00000000, 0x00010000):
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b = bios.read(1)
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if not b:
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image.write(0xff.to_bytes(1, "big"))
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else:
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image.write(b)
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bitstream.close()
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bios.close()
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image.close()
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print("Flashing bitstream (+bios)")
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prog.flash(0x0, "build/"+target+"/image.bin")
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=lattice_ice40up5k_evn.Platform, description="LiteX SoC on Lattice iCE40UP5k EVN breakout board.")
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parser.add_target_argument("--sys-clk-freq", default=12e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--bios-flash-offset", default="0x20000", help="BIOS offset in SPI Flash.")
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parser.add_target_argument("--flash", action="store_true", help="Flash Bitstream.")
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args = parser.parse_args()
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soc = BaseSoC(
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bios_flash_offset = int(args.bios_flash_offset, 0),
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sys_clk_freq = args.sys_clk_freq,
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**parser.soc_argdict
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)
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.flash:
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flash(args.bios_flash_offset)
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if __name__ == "__main__":
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main()
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