89 lines
3.0 KiB
Python
Executable File
89 lines
3.0 KiB
Python
Executable File
#!/usr/bin/env python3
|
|
|
|
#
|
|
# This file is part of LiteX-Boards.
|
|
#
|
|
# Copyright (c) 2021 Miodrag Milanovic <mmicko@gmail.com>
|
|
# SPDX-License-Identifier: BSD-2-Clause
|
|
|
|
from migen import *
|
|
from migen.genlib.resetsync import AsyncResetSynchronizer
|
|
|
|
from litex.gen import *
|
|
|
|
from litex_boards.platforms import sipeed_tang_primer
|
|
|
|
from litex.build.generic_platform import *
|
|
|
|
from litex.soc.cores.clock import *
|
|
from litex.soc.integration.soc_core import *
|
|
from litex.soc.integration.builder import *
|
|
from litex.soc.cores.led import LedChaser
|
|
|
|
|
|
# CRG ----------------------------------------------------------------------------------------------
|
|
|
|
class _CRG(LiteXModule):
|
|
def __init__(self, platform, sys_clk_freq):
|
|
self.rst = Signal()
|
|
self.cd_sys = ClockDomain()
|
|
|
|
# # #
|
|
|
|
# Clk / Rst.
|
|
clk24 = platform.request("clk24")
|
|
rst_n = platform.request("user_btn", 0)
|
|
|
|
self.comb += self.cd_sys.clk.eq(clk24)
|
|
self.specials += AsyncResetSynchronizer(self.cd_sys, ~rst_n | self.rst)
|
|
|
|
# BaseSoC ------------------------------------------------------------------------------------------
|
|
|
|
class BaseSoC(SoCCore):
|
|
def __init__(self, sys_clk_freq=24e6, with_led_chaser=True, **kwargs):
|
|
platform = sipeed_tang_primer.Platform()
|
|
|
|
# CRG --------------------------------------------------------------------------------------
|
|
self.crg = _CRG(platform, sys_clk_freq)
|
|
|
|
# SoCCore ----------------------------------------------------------------------------------
|
|
if kwargs.get("cpu_type", "vexriscv") == "vexriscv":
|
|
kwargs["cpu_variant"] = "minimal"
|
|
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Tang Primer", **kwargs)
|
|
|
|
# Leds -------------------------------------------------------------------------------------
|
|
if with_led_chaser:
|
|
self.leds = LedChaser(
|
|
pads = platform.request_all("user_led"),
|
|
sys_clk_freq = sys_clk_freq)
|
|
|
|
# Build --------------------------------------------------------------------------------------------
|
|
|
|
def main():
|
|
from litex.build.parser import LiteXArgumentParser
|
|
parser = LiteXArgumentParser(platform=sipeed_tang_primer.Platform, description="LiteX SoC on Tang Primer.")
|
|
parser.add_target_argument("--flash", action="store_true", help="Flash Bitstream.")
|
|
parser.add_target_argument("--sys-clk-freq", default=24e6, type=float, help="System clock frequency.")
|
|
args = parser.parse_args()
|
|
|
|
soc = BaseSoC(
|
|
sys_clk_freq = args.sys_clk_freq,
|
|
**parser.soc_argdict
|
|
)
|
|
|
|
builder = Builder(soc, **parser.builder_argdict)
|
|
if args.build:
|
|
builder.build(**parser.toolchain_argdict)
|
|
|
|
if args.load:
|
|
prog = soc.platform.create_programmer()
|
|
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
|
|
|
|
if args.flash:
|
|
prog = soc.platform.create_programmer()
|
|
prog.load_bitstream(builder.get_bitstream_filename(mode="flash", ext=".bin")) # FIXME
|
|
|
|
|
|
if __name__ == "__main__":
|
|
main()
|