163 lines
6.3 KiB
Python
Executable File
163 lines
6.3 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.gen import *
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from litex.build.io import DDROutput
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from litex_boards.platforms import terasic_de2_115
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from litex.soc.cores.clock import CycloneIVPLL
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from litex.soc.cores.led import LedChaser
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litedram.modules import IS42S16320
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from litedram.phy import GENSDRPHY
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from liteeth.phy.mii import LiteEthPHYMII
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_sys_ps = ClockDomain()
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# # #
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# Clk / Rst
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clk50 = platform.request("clk50")
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# PLL
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self.pll = pll = CycloneIVPLL(speedgrade="-7")
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(clk50, 50e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
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# SDRAM clock
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self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps"))
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=50e6,
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with_ethernet = False,
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with_etherbone = False,
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with_sdcard = False,
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with_led_chaser = True,
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ethernet_phy = 0,
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etherbone_ip = "192.168.1.50",
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etherbone_phy = 1,
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**kwargs,
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):
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platform = terasic_de2_115.Platform()
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# CRG --------------------------------------------------------------------------------------
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self.crg = _CRG(platform, sys_clk_freq)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on DE2-115", **kwargs)
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# SDR SDRAM --------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.sdrphy,
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module = IS42S16320(self.clk_freq, "1:1"),
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# Add debug interface if the CPU has one ---------------------------------------------------
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if hasattr(self.cpu, "debug_bus"):
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self.register_mem(
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name = "vexriscv_debug",
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address = 0xF00F0000,
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interface = self.cpu.debug_bus,
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size = 0x100,
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)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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pads = platform.request_all("user_led"), sys_clk_freq=sys_clk_freq
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)
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self.leds.add_pwm()
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# SD Card ----------------------------------------------------------------------------------
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if with_sdcard:
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self.add_sdcard()
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# Ethernet ---------------------------------------------------------------------------------
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if with_ethernet:
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# Ethernet PHY
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self.submodules.ethphy = LiteEthPHYMII(
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clock_pads = platform.request("eth_clocks", ethernet_phy),
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pads = platform.request("eth", ethernet_phy),
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)
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self.add_ethernet(
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phy = self.ethphy,
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phy_cd = "ethphy_eth" if with_etherbone else "eth",
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dynamic_ip = True,
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)
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if with_etherbone:
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# Ethernet PHY
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self.submodules.ethbphy = LiteEthPHYMII(
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clock_pads = platform.request("eth_clocks", etherbone_phy),
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pads = platform.request("eth", etherbone_phy),
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)
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self.add_etherbone(
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phy = self.ethbphy,
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phy_cd = "ethbphy_eth" if with_ethernet else "eth",
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ip_address = etherbone_ip,
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)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=terasic_de2_115.Platform, description="LiteX SoC on DE2-115.")
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parser.add_target_argument("--sys-clk-freq", default=50e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--with-led-chaser", action="store_true", help="Enable LED chaser.")
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parser.add_target_argument("--with-sdcard", action="store_true", help="Enable SD card support.")
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parser.add_target_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
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parser.add_target_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
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parser.add_target_argument("--etherbone-ip", default="192.168.48.100", help="Etherbone IP address.")
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parser.add_target_argument("--etherbone-phy", default=1, type=int, help="Etherbone PHY (0 or 1).")
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parser.add_target_argument("--ethernet-phy", default=0, type=int, help="Ethernet PHY (0 or 1).")
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = args.sys_clk_freq,
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with_sdcard = args.with_sdcard,
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with_ethernet = args.with_ethernet,
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with_etherbone = args.with_etherbone,
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with_led_chaser = args.with_led_chaser,
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etherbone_ip = args.etherbone_ip,
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etherbone_phy = args.etherbone_phy,
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ethernet_phy = args.ethernet_phy,
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**parser.soc_argdict,
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)
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if __name__ == "__main__":
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main()
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