238 lines
10 KiB
Markdown
238 lines
10 KiB
Markdown
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/ / (_) /____ | |/_/___/ _ )___ ___ ________/ /__
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/ /__/ / __/ -_)> </___/ _ / _ \/ _ `/ __/ _ (_-<
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/____/_/\__/\__/_/|_| /____/\___/\_,_/_/ \_,_/___/
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LiteX boards files
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Copyright 2012-2022 / LiteX-Hub community
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[](https://github.com/litex-hub/litex-boards/actions) 
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[> Intro
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--------
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<figure>
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<p align="center">
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<img src="https://user-images.githubusercontent.com/1450143/88511626-73792100-cfe5-11ea-8d3e-dbeea6314e15.JPG">
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</p>
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<figcaption>
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<p align="center">
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From the very tiny Fomu to large PCIe accelerator boards....
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</p>
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</figcaption>
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</figure>
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This repository contains the platforms/targets currently supported by LiteX:
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- The platform provides the definition of the board: IOs, constraints, clocks, components + methods to load and flash the bitstream to it.
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- The target provides a LiteX base design for the board that allows you to create a SoC (with or without a CPU) and integrate easily all the base components of your board: Ethernet, DRAM, PCIe, SPIFlash, SDCard, Leds, GPIOs, etc...
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The targets can be used as a base to build more complex or custom SoCs. They are are for example directly reused by the [Linux-on-LiteX-VexRiscv](https://github.com/litex-hub/linux-on-litex-vexriscv) project that is just using a specific configuration (Linux-capable CPU, additional peripherals). Basing your design on provided targets allows to to reduce code duplication between very various projects.
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First make sure to install LiteX correctly by following the [installation guide](https://github.com/enjoy-digital/litex/wiki/Installation) and have a look at the [LiteX's wiki](https://github.com/enjoy-digital/litex/wiki) for [tutorials](https://github.com/enjoy-digital/litex/wiki/Tutorials-Resources), [examples of projects](https://github.com/enjoy-digital/litex/wiki/Projects) and more information to use/build FPGA designs with it.
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Each target provides a default configuration with a CPU, ROM, SRAM, UART, DRAM (if available), Ethernet (if available), etc... that can be simply built and loaded to the FPGA with:
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$ python3 -m litex_boards.targets.<board> --build --load
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You can then open a terminal on the main UART of the board and interact with the LiteX BIOS:
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<p align="center"><img src="https://raw.githubusercontent.com/enjoy-digital/litex/master/doc/bios_screenshot.png"></p>
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**Build/Compilation behavior:**
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- python3 -m litex_boards.targets.board : Test LiteX/Migen syntax but does not generate anything.
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- Add `--build` to generate the SoC/Software headers and run the Software/Gateware compilation.
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- Add `--no-compile` to disable the Softwate/Gateware compilation.
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- Add `--no-compile-software` to disable the Software compilation.
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- Add `--no-compile-gateware` to disable the Gateware compilation.
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But this is just the starting point to create your own hardware! You can then:
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- Change the CPU: add `--cpu-type=lm32, microwatt, serv, rocket, etc... `
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- Change the Bus standard: add `--bus-standard=wishbone, axi-lite`
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- Enable components: add `--with-ethernet --with-etherbone --with-sdcard etc...`
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- [Load application code to the CPU](https://github.com/enjoy-digital/litex/wiki/Load-Application-Code-To-CPU) over UART/Ethernet/SDCard, etc...
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- Create a bridge with your computer to easily [access the main bus of your SoC](https://github.com/enjoy-digital/litex/wiki/Use-Host-Bridge-to-control-debug-a-SoC).
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- Add a Logic Analyzer to your SoC to easily [observe/debug your design](https://github.com/enjoy-digital/litex/wiki/Use-LiteScope-To-Debug-A-SoC).
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- Simulate your SoC and interact with it at decent speed with [LiteX Sim](https://github.com/enjoy-digital/litex/blob/master/litex/tools/litex_sim.py)/Verilator.
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- Integrate external cores/CPU to create your own design.
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- etc...
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Please use `python3 -m litex_boards.targets.<board> --help` to see the pre-built various possibilities.
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Hoping you will find this useful and enjoy it, please contribute back if you make improvements that could be useful to others or find issues!
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**A question or want to get in touch? Our IRC channel is [#litex at irc.libera.chat](https://web.libera.chat/#litex)**
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[> Supported boards
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-------------------
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LiteX-Boards currently supports > 120 boards from very various FPGA Vendors (Xilinx, Intel, Lattice, Efinix, Gowin, etc...)!
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Some of these boards are fully open-hardware boards (Fomu, NeTV2, OrangeCrab, Butterstick, etc...) with FPGAs often supported by the open-source toolchains, some of them are repurposed off-the-shelf hardware (Colorlight 5A/I5/I9, SQRL Acorn CLE 215+, FK33, Siglent SDS1104X-E, Decklink Mini 4k, etc...) and we also of course support popular/regular FPGA dev boards :)
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Most of the peripherals present are generally supported: DRAM, UART, Ethernet, SPI-Flash, SDCard, PCIe, SATA, etc... making LiteX-Boards' targets hopefully a good base infrastructure to create your own custom SoCs!
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> **Note:** All boards with >= 32MB of memory and enough logic can be considered as Linux Capable, have a look at [LiteX-on-LiteX-Vexriscv](https://github.com/litex-hub/linux-on-litex-vexriscv) project to try Linux on your FPGA board!
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<figure>
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<p align="center">
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<img src="https://user-images.githubusercontent.com/1450143/156173620-355c6f1d-87dc-4dda-be45-910bf379ae9a.jpg">
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</p>
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<figcaption>
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<p align="center">
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Some of the suported boards, see yours? Give LiteX-Boards a try!
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</p>
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</figcaption>
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</figure>
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[> Boards list
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---------------
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├── adi_adrv2crr_fmc
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├── adi_plutosdr
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├── alchitry_au
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├── alchitry_mojo
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├── aliexpress_stlv7325
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├── aliexpress_xc7k420t
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├── alinx_ax7010
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├── alinx_axu2cga
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├── antmicro_artix_dc_scm
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├── antmicro_datacenter_ddr4_test_board
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├── antmicro_lpddr4_test_board
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├── arduino_mkrvidor4000
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├── avalanche
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├── avnet_aesku40
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├── berkeleylab_marblemini
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├── berkeleylab_marble
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├── camlink_4k
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├── colorlight_5a_75b
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├── colorlight_5a_75e
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├── colorlight_i5
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├── decklink_intensity_pro_4k
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├── decklink_mini_4k
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├── decklink_quad_hdmi_recorder
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├── digilent_arty
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├── digilent_arty_s7
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├── digilent_arty_z7
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├── digilent_atlys
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├── digilent_basys3
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├── digilent_cmod_a7
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├── digilent_genesys2
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├── digilent_nexys4ddr
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├── digilent_nexys4
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├── digilent_nexys_video
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├── digilent_pynq_z1
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├── digilent_zedboard
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├── digilent_zybo_z7
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├── ebaz4205
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├── efinix_t8f81_dev_kit
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├── efinix_titanium_ti60_f225_dev_kit
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├── efinix_trion_t120_bga576_dev_kit
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├── efinix_trion_t20_bga256_dev_kit
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├── efinix_trion_t20_mipi_dev_kit
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├── efinix_xyloni_dev_kit
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├── ego1
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├── enclustra_mercury_kx2
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├── enclustra_mercury_xu5
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├── fairwaves_xtrx
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├── fpc_iii
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├── gsd_butterstick
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├── gsd_orangecrab
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├── hackaday_hadbadge
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├── hpcstore_xc7k420t
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├── icebreaker_bitsy
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├── icebreaker
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├── jungle_electronics_fireant
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├── kosagi_fomu_evt
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├── kosagi_fomu_hacker
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├── kosagi_fomu_pvt
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├── kosagi_netv2
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├── krtkl_snickerdoodle
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├── lambdaconcept_ecpix5
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├── lambdaconcept_pcie_screamer_m2
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├── lambdaconcept_pcie_screamer
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├── lattice_crosslink_nx_evn
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├── lattice_crosslink_nx_vip
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├── lattice_ecp5_evn
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├── lattice_ecp5_vip
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├── lattice_ice40up5k_evn
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├── lattice_machxo3
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├── lattice_versa_ecp5
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├── limesdr_mini_v2
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├── linsn_rv901t
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├── litex_acorn_baseboard
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├── logicbone
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├── machdyne_krote
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├── machdyne_schoko
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├── marblemini
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├── marble
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├── micronova_mercury2
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├── mist
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├── mnt_rkx7
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├── muselab_icesugar_pro
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├── muselab_icesugar
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├── myminieye_runber
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├── newae_cw305
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├── numato_aller
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├── numato_mimas_a7
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├── numato_nereid
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├── numato_tagus
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├── pano_logic_g2
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├── qmtech_10cl006
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├── qmtech_5cefa2
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├── qmtech_ep4cex5
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├── qmtech_ep4cgx150
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├── qmtech_wukong
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├── qmtech_xc7a35t
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├── quicklogic_quickfeather
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├── qwertyembedded_beaglewire
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├── radiona_ulx3s
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├── rcs_arctic_tern_bmc_card
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├── redpitaya
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├── rz_easyfpga
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├── saanlima_pipistrello
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├── scarabhardware_minispartan6
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├── seeedstudio_spartan_edge_accelerator
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├── siglent_sds1104xe
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├── sipeed_tang_nano_4k
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├── sipeed_tang_nano_9k
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├── sipeed_tang_nano
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├── sipeed_tang_primer_20k
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├── sipeed_tang_primer
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├── sqrl_acorn
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├── sqrl_fk33
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├── sqrl_xcu1525
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├── taobao_a_e115fb
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├── terasic_de0nano
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├── terasic_de10lite
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├── terasic_de10nano
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├── terasic_de1soc
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├── terasic_de2_115
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├── terasic_deca
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├── terasic_sockit
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├── tinyfpga_bx
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├── trellisboard
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├── trenz_c10lprefkit
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├── trenz_cyc1000
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├── trenz_max1000
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├── trenz_te0725
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├── trenz_tec0117
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├── tul_pynq_z2
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├── xilinx_ac701
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├── xilinx_alveo_u250
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├── xilinx_alveo_u280
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├── xilinx_kc705
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├── xilinx_kcu105
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├── xilinx_kv260
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├── xilinx_sp605
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├── xilinx_vc707
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├── xilinx_vcu118
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├── xilinx_zcu102
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├── xilinx_zcu104
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├── xilinx_zcu106
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├── xilinx_zcu216
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└── ztex213
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