385 lines
12 KiB
Python
385 lines
12 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2018-2019 Rohit Singh <rohit@rohitksingh.in>
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# Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import Xilinx7SeriesPlatform
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from litex.build.openocd import OpenOCD
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk100", 0, Pins("F22"), IOStandard("LVCMOS33")),
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("clk150", 0,
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Subsignal("p", Pins("G24"), IOStandard("TMDS_33")),
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Subsignal("n", Pins("F24"), IOStandard("TMDS_33"))
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),
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("cpu_reset", 0, Pins("C26"), IOStandard("LVCMOS33"), Misc("PULLDOWN=True")), # Active high, pulldown needed.
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# Leds (activive-low)
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("rgb_led", 0,
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Subsignal("r", Pins("J26")),
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Subsignal("g", Pins("H26")),
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Subsignal("b", Pins("G26")),
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IOStandard("LVCMOS33"),
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),
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# FAN
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("fan", 0, Pins("J25"), IOStandard("LVCMOS33")),
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# Serial
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("serial", 0,
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Subsignal("tx", Pins("H22")),
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Subsignal("rx", Pins("K22")),
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Subsignal("rts", Pins("L22")),
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Subsignal("cts", Pins("L23")),
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Subsignal("cbus0", Pins("K23")),
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IOStandard("LVCMOS33")
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),
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# XADC
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("xadc", 0,
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Subsignal("adc_p", Pins("C16 A18 B17")),
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Subsignal("adc_n", Pins("B16 A19 A17")),
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Subsignal("v_p", Pins("N12")),
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Subsignal("v_n", Pins("P11")),
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),
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# DDR3 SDRAM
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("ddram", 0,
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Subsignal("a", Pins(
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"AF7 AE7 AC7 AB7 AA7 AC8 AC9 AA9",
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"AD8 V9 Y11 Y7 W10 Y8 Y10 W9"),
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IOStandard("SSTL135")),
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Subsignal("ba", Pins("AA8 AD9 AB9"), IOStandard("SSTL135")),
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Subsignal("ras_n", Pins("AC13"), IOStandard("SSTL135")),
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Subsignal("cas_n", Pins("AC12"), IOStandard("SSTL135")),
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Subsignal("we_n", Pins("AA13"), IOStandard("SSTL135")),
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Subsignal("cs_n", Pins("AB12"), IOStandard("SSTL135")),
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Subsignal("dm", Pins(
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"W16 AD18 AE15 AB15 AD1 AC3 Y3 V6"),
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IOStandard("SSTL135")),
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Subsignal("dq", Pins(
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"V19 V16 Y17 V14 V17 V18 W14 W15",
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"AB17 AB19 AC18 AC19 AA19 AA20 AC17 AD19",
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"AD16 AD15 AF20 AE17 AF17 AF19 AF14 AF15",
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"AB16 AA15 AA14 AC14 AA18 AA17 AD14 AB14",
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"AE3 AE6 AE2 AF3 AD4 AE5 AE1 AF2",
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"AB6 Y6 AB4 AC4 AC6 AD6 Y5 AA4",
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"AB2 AC2 V1 W1 V2 AA3 Y1 Y2",
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"V4 V3 U2 U1 U7 W3 U6 U5"),
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IOStandard("SSTL135_T_DCI")),
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Subsignal("dqs_p", Pins("W18 AD20 AE18 Y15 AF5 AA5 AB1 W6"),
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IOStandard("DIFF_SSTL135")),
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Subsignal("dqs_n", Pins("W19 AE20 AF18 Y16 AF4 AB5 AC1 W5"),
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IOStandard("DIFF_SSTL135")),
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Subsignal("clk_p", Pins("V11"), IOStandard("DIFF_SSTL135")),
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Subsignal("clk_n", Pins("W11"), IOStandard("DIFF_SSTL135")),
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Subsignal("cke", Pins("AA10"), IOStandard("SSTL135")),
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Subsignal("odt", Pins("AD13"), IOStandard("SSTL135")),
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Subsignal("reset_n", Pins("AA2"), IOStandard("SSTL135")),
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Misc("SLEW=FAST"),
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),
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# SPIFlash
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("spiflash", 0, # clock needs to be accessed through STARTUPE2
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Subsignal("cs_n", Pins("C23")),
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Subsignal("mosi", Pins("B24")),
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Subsignal("miso", Pins("A25")),
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Subsignal("wp", Pins("B22")),
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Subsignal("hold", Pins("A22")),
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IOStandard("LVCMOS33"),
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),
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("spiflash4x", 0, # clock needs to be accessed through STARTUPE2
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Subsignal("cs_n", Pins("C23")),
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Subsignal("dq", Pins("B24", "A25", "B22", "A22")),
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IOStandard("LVCMOS33")
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),
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# SDCard
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("sdcard", 0,
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Subsignal("cmd", Pins("H24")),
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Subsignal("clk", Pins("G22")),
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Subsignal("dat", Pins("F25 E25 J23 H23")),
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IOStandard("LVCMOS33")
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),
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# PCIe
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("pcie_x1", 0,
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Subsignal("rst_n", Pins("E21"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")),
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Subsignal("clk_p", Pins("K6")),
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Subsignal("clk_n", Pins("K5")),
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Subsignal("rx_p", Pins("J4")),
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Subsignal("rx_n", Pins("J3")),
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Subsignal("tx_p", Pins("H2")),
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Subsignal("tx_n", Pins("H1"))
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),
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("pcie_x2", 0,
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Subsignal("rst_n", Pins("E21"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")),
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Subsignal("clk_p", Pins("K6")),
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Subsignal("clk_n", Pins("K5")),
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Subsignal("rx_p", Pins("J4 L4")),
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Subsignal("rx_n", Pins("J3 L3")),
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Subsignal("tx_p", Pins("H2 K2")),
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Subsignal("tx_n", Pins("H1 K1"))
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),
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("pcie_x4", 0,
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Subsignal("rst_n", Pins("E21"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")),
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Subsignal("clk_p", Pins("K6")),
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Subsignal("clk_n", Pins("K5")),
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Subsignal("rx_p", Pins("J4 L4 N4 R4")),
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Subsignal("rx_n", Pins("J3 L3 N3 R3")),
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Subsignal("tx_p", Pins("H2 K2 M2 P2")),
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Subsignal("tx_n", Pins("H1 K1 M1 P1"))
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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("HPC", {
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# FMC GTP Section
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"DP0_M2C_P" : "G4",
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"DP0_M2C_N" : "G3",
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"DP1_M2C_P" : "E4",
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"DP1_M2C_N" : "E3",
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"DP2_M2C_P" : "C4",
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"DP2_M2C_N" : "C3",
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"DP3_M2C_P" : "B6",
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"DP3_M2C_N" : "B5",
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"GBTCLK0_M2C_P" : "F6",
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"GBTCLK0_M2C_N" : "F5",
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"GBTCLK1_M2C_P" : "D6",
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"GBTCLK1_M2C_N" : "D5",
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"DP0_C2M_P" : "F2",
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"DP0_C2M_N" : "F1",
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"DP1_C2M_P" : "D2",
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"DP1_C2M_N" : "D1",
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"DP2_C2M_P" : "B2",
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"DP2_C2M_N" : "B1",
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"DP3_C2M_P" : "A4",
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"DP3_C2M_N" : "A3",
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# FMC LA Bank GPIOs
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"LA00_P" : "AA23",
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"LA00_N" : "AB24",
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"LA01_P" : "Y23",
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"LA01_N" : "AA24",
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"LA02_P" : "AD26",
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"LA02_N" : "AE26",
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"LA03_P" : "AA25",
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"LA03_N" : "AB25",
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"LA04_P" : "AD25",
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"LA04_N" : "AE25",
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"LA05_P" : "W25",
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"LA05_N" : "W26",
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"LA06_P" : "Y25",
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"LA06_N" : "Y26",
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"LA07_P" : "V23",
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"LA07_N" : "V24",
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"LA08_P" : "U26",
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"LA08_N" : "V26",
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"LA09_P" : "W20",
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"LA09_N" : "Y21",
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"LA10_P" : "V21",
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"LA10_N" : "W21",
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"LA11_P" : "L19",
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"LA11_N" : "L20",
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"LA12_P" : "M17",
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"LA12_N" : "L18",
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"LA13_P" : "K20",
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"LA13_N" : "J20",
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"LA14_P" : "J18",
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"LA14_N" : "J19",
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"LA15_P" : "U17",
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"LA15_N" : "T17",
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"LA16_P" : "T18",
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"LA16_N" : "T19",
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"LA17_P" : "E18",
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"LA17_N" : "D18",
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"LA18_P" : "F17",
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"LA18_N" : "E17",
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"LA19_P" : "H16",
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"LA19_N" : "G16",
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"LA20_P" : "K16",
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"LA20_N" : "K17",
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"LA21_P" : "D19",
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"LA21_N" : "D20",
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"LA22_P" : "C19",
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"LA22_N" : "B19",
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"LA23_P" : "C17",
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"LA23_N" : "C18",
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"LA24_P" : "D15",
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"LA24_N" : "D16",
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"LA25_P" : "F19",
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"LA25_N" : "E20",
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"LA26_P" : "J15",
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"LA26_N" : "J16",
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"LA27_P" : "G15",
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"LA27_N" : "F15",
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"LA28_P" : "G17",
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"LA28_N" : "F18",
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"LA29_P" : "E15",
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"LA29_N" : "E16",
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"LA30_P" : "H17",
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"LA30_N" : "H18",
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"LA31_P" : "G19",
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"LA31_N" : "F20",
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"LA32_P" : "H19",
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"LA32_N" : "G20",
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"LA33_P" : "L17",
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"LA33_N" : "K18",
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# FMC HA Bank GPIOs
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"HA00_P" : "P23",
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"HA00_N" : "N23",
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"HA01_P" : "N21",
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"HA01_N" : "N22",
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"HA02_P" : "AB22",
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"HA02_N" : "AC22",
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"HA03_P" : "AD23",
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"HA03_N" : "AD24",
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"HA04_P" : "N19",
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"HA04_N" : "M20",
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"HA05_P" : "R18",
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"HA05_N" : "P18",
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"HA06_P" : "P16",
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"HA06_N" : "N17",
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"HA07_P" : "R16",
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"HA07_N" : "R17",
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"HA08_P" : "U19",
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"HA08_N" : "U20",
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"HA09_P" : "N18",
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"HA09_N" : "M19",
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"HA10_P" : "T20",
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"HA10_N" : "R20",
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"HA11_P" : "P19",
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"HA11_N" : "P20",
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"HA12_P" : "T24",
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"HA12_N" : "T25",
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"HA13_P" : "U24",
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"HA13_N" : "U25",
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"HA14_P" : "R26",
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"HA14_N" : "P26",
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"HA15_P" : "P24",
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"HA15_N" : "N24",
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"HA16_P" : "R25",
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"HA16_N" : "P25",
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"HA17_P" : "M21",
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"HA17_N" : "M22",
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"HA18_P" : "N26",
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"HA18_N" : "M26",
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"HA19_P" : "K25",
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"HA19_N" : "K26",
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"HA20_P" : "M25",
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"HA20_N" : "L25",
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"HA21_P" : "M24",
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"HA21_N" : "L24",
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"HA22_P" : "T22",
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"HA22_N" : "T23",
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"HA23_P" : "U22",
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"HA23_N" : "V22",
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# FMC HB Bank GPIOs
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"HB00_P" : "E10",
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"HB00_N" : "D10",
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"HB01_P" : "F14",
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"HB01_N" : "F13",
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"HB02_P" : "H14",
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"HB02_N" : "G14",
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"HB03_P" : "J13",
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"HB03_N" : "H13",
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"HB04_P" : "B14",
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"HB04_N" : "A14",
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"HB05_P" : "B15",
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"HB05_N" : "A15",
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"HB06_P" : "C12",
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"HB06_N" : "C11",
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"HB07_P" : "G10",
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"HB07_N" : "G9",
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"HB08_P" : "E13",
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"HB08_N" : "E12",
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"HB09_P" : "D14",
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"HB09_N" : "D13",
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"HB10_P" : "C9",
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"HB10_N" : "B9",
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"HB11_P" : "A13",
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"HB11_N" : "A12",
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"HB12_P" : "B10",
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"HB12_N" : "A10",
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"HB13_P" : "B12",
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"HB13_N" : "B11",
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"HB14_P" : "F9",
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"HB14_N" : "F8",
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"HB15_P" : "E11",
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"HB15_N" : "D11",
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"HB16_P" : "D9",
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"HB16_N" : "D8",
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"HB17_P" : "G11",
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"HB17_N" : "F10",
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"HB18_P" : "G12",
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"HB18_N" : "F12",
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"HB19_P" : "A9",
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"HB19_N" : "A8",
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"HB20_P" : "J11",
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"HB20_N" : "J10",
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"HB21_P" : "H9",
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"HB21_N" : "H8",
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# FMC Clock and Misc signals
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"CLK0_M2C_P" : "Y22",
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"CLK0_M2C_N" : "AA22",
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"CLK1_M2C_P" : "AC23",
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"CLK1_M2C_N" : "AC24",
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"CLK2_BIDIR_P" : "R22",
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"CLK2_BIDIR_N" : "R23",
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"CLK3_BIDIR_P" : "R21",
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"CLK3_BIDIR_N" : "P21",
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"CLK_DIR" : "D23",
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"PG_C2M" : "D26",
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"PG_M2C" : "E26",
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"FMC_SCL" : "C21",
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"FMC_SDA" : "B21",
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"FMC_PRSNT" : "B26",
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}
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(Xilinx7SeriesPlatform):
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default_clk_name = "clk100"
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default_clk_period = 1e9/100e6
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def __init__(self, toolchain="vivado"):
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Xilinx7SeriesPlatform.__init__(self, "xc7k160t-fbg676-1", _io, _connectors, toolchain=toolchain)
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self.add_platform_command("""
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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""")
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self.toolchain.bitstream_commands = [
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"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
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"set_property BITSTREAM.CONFIG.CONFIGRATE 16 [current_design]",
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"set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]"
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]
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self.toolchain.additional_commands = \
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["write_cfgmem -force -format bin -interface spix4 -size 16 "
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"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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def create_programmer(self):
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return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc7k160t.bit")
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def do_finalize(self, fragment):
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Xilinx7SeriesPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
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self.add_period_constraint(self.lookup_request("clk150", loose=True), 1e9/150e6)
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