157 lines
6.2 KiB
Python
157 lines
6.2 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2022 Andrew Elbert Wilson <Andrew.E.Wilson@ieee.org>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxUSPPlatform, VivadoProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("sys_clk100", 0,
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Subsignal("p", Pins("T24"), IOStandard("LVDS")),
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Subsignal("n", Pins("U24"), IOStandard("LVDS"))
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),
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("ddr_clk100", 0,
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Subsignal("p", Pins("AD20"), IOStandard("LVDS")),
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Subsignal("n", Pins("AE20"), IOStandard("LVDS"))
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),
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#NO RESET, maybe use okHOST USB later
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#("cpu_reset", 0, Pins("AN8"), IOStandard("LVCMOS18")),
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# Leds
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("user_led", 0, Pins("G19"), IOStandard("LVCMOS18")),
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("user_led", 1, Pins("B16"), IOStandard("LVCMOS18")),
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("user_led", 2, Pins("F22"), IOStandard("LVCMOS18")),
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("user_led", 3, Pins("E22"), IOStandard("LVCMOS18")),
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("user_led", 4, Pins("M24"), IOStandard("LVCMOS18")),
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("user_led", 5, Pins("G22"), IOStandard("LVCMOS18")),
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# Opal Kelly Host USBC interface
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("okHost", 0, # Uses the FrontPanel API
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Subsignal("okAA", Pins("T19")),
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Subsignal("okHU", Pins("U20 U26 T22")),
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Subsignal("okUH", Pins("V23 T23 U22 U25 U21")),
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Subsignal("okUHU", Pins(
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"P26 P25 R26 R25 R23 R22 P21 P20",
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"R21 R20 P23 N23 T25 N24 N22 V26",
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"N19 V21 N21 W20 W26 W19 Y25 Y26",
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"Y22 V22 W21 AA23 Y23 AA24 W25 AA25")),
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IOStandard("LVCMOS18"),
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Misc("SLEW=FAST"),
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),
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# TODO: Add SMA & SFP+
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# DDR4 SDRAM
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("ddram", 0,
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Subsignal("a", Pins(
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"AD18 AE17 AB17 AE18 AD19 AF17 Y17 AE16",
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"AA17 AC17 AC19 AC16 AF20 AD16"),
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IOStandard("SSTL12_DCI")),
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Subsignal("ba", Pins("AC18 AF18"), IOStandard("SSTL12_DCI")),
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Subsignal("bg", Pins("AB19"), IOStandard("SSTL12_DCI")),
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Subsignal("ras_n", Pins("AA18"), IOStandard("SSTL12_DCI")),
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Subsignal("cas_n", Pins("AF19"), IOStandard("SSTL12_DCI")),
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Subsignal("we_n", Pins("AA19"), IOStandard("SSTL12_DCI")),
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Subsignal("cs_n", Pins("AF22"), IOStandard("SSTL12_DCI")),
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Subsignal("act_n", Pins("Y18"), IOStandard("SSTL12_DCI")),
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Subsignal("dm", Pins("AE25 AE22"),
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IOStandard("POD12_DCI")),
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Subsignal("dq", Pins(
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"AF24 AB25 AB26 AC24 AF25 AB24 AD24 AD25",
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"AB21 AE21 AE23 AD23 AC23 AD21 AC22 AC21"),
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IOStandard("POD12_DCI"),
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Misc("PRE_EMPHASIS=RDRV_240"),
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Misc("EQUALIZATION=EQ_LEVEL2")),
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Subsignal("dqs_p", Pins("AC26 AA22"),
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IOStandard("DIFF_POD12_DCI"),
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Misc("PRE_EMPHASIS=RDRV_240"),
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Misc("EQUALIZATION=EQ_LEVEL2")),
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Subsignal("dqs_n", Pins("AD26 AB22"),
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IOStandard("DIFF_POD12_DCI"),
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Misc("PRE_EMPHASIS=RDRV_240"),
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Misc("EQUALIZATION=EQ_LEVEL2")),
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Subsignal("clk_p", Pins("Y20"), IOStandard("DIFF_SSTL12_DCI")),
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Subsignal("clk_n", Pins("Y21"), IOStandard("DIFF_SSTL12_DCI")),
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Subsignal("cke", Pins("AA20"), IOStandard("SSTL12_DCI")),
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Subsignal("odt", Pins("AB20"), IOStandard("SSTL12_DCI")),
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Subsignal("reset_n", Pins("AE26"), IOStandard("LVCMOS12")),
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Misc("SLEW=FAST"),
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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# TODO: SYZYGY Connectors & SYZYGY to PMODS!
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_connectors = [
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("pmod1", "AC14 AC13 AF15 AF14 AF13 AE13 H13 J13"),
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("pmod2", "AB15 AB16 W14 J14 AE15 W15 Y15 J15"),
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("pmod3", "G14 H14 W13 W12 AA13 Y13 H12 J12"),
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("pmod4", "AD14 AD13 W16 AD15 AB14 AA14 Y16 AA15"),
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]
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def dvi_pmod_io(pmoda,pmodb):
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return [
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("dvi", 0,
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Subsignal("clk", Pins(f"{pmodb}:1")),
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Subsignal("de", Pins(f"{pmodb}:6")),
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Subsignal("hsync", Pins(f"{pmodb}:3")),
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Subsignal("vsync", Pins(f"{pmodb}:7")),
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Subsignal("b", Pins(f"{pmoda}:5 {pmoda}:1 {pmoda}:4 {pmoda}:0")),
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Subsignal("g", Pins(f"{pmoda}:7 {pmoda}:3 {pmoda}:6 {pmoda}:2")),
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Subsignal("r", Pins(f"{pmodb}:2 {pmodb}:5 {pmodb}:4 {pmodb}:0")),
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IOStandard("LVCMOS33"),
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)
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]
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_dvi_pmod_io = dvi_pmod_io("pmod2","pmod1") # SDCARD PMOD on JD.
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def sdcard_pmod_io(pmod):
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return [
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# SDCard PMOD:
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# - https://store.digilentinc.com/pmod-microsd-microsd-card-slot/
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# - https://github.com/antmicro/arty-expansion-board
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("spisdcard", 0,
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Subsignal("clk", Pins(f"{pmod}:3")),
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Subsignal("mosi", Pins(f"{pmod}:1"), Misc("PULLUP True")),
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Subsignal("cs_n", Pins(f"{pmod}:0"), Misc("PULLUP True")),
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Subsignal("miso", Pins(f"{pmod}:2"), Misc("PULLUP True")),
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Misc("SLEW=FAST"),
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IOStandard("LVCMOS33"),
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),
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("sdcard", 0,
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Subsignal("data", Pins(f"{pmod}:2 {pmod}:4 {pmod}:5 {pmod}:0"), Misc("PULLUP True")),
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Subsignal("cmd", Pins(f"{pmod}:1"), Misc("PULLUP True")),
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Subsignal("clk", Pins(f"{pmod}:3")),
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Subsignal("cd", Pins(f"{pmod}:6")),
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Misc("SLEW=FAST"),
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IOStandard("LVCMOS33"),
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),
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]
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_sdcard_pmod_io = sdcard_pmod_io("pmod3") # SDCARD PMOD on JD.
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxUSPPlatform):
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default_clk_name = "sys_clk100"
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default_clk_period = 1e9/100e6
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def __init__(self, toolchain="vivado"):
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XilinxUSPPlatform.__init__(self, "xcau25p-ffvb676-2-e", _io, _connectors, toolchain=toolchain)
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def create_programmer(self):
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return VivadoProgrammer()
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def do_finalize(self, fragment):
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XilinxUSPPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("sys_clk100", loose=True), 1e9/100e6)
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self.add_period_constraint(self.lookup_request("ddr_clk100", loose=True), 1e9/100e6)
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self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 64]")
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