62 lines
1.9 KiB
Python
62 lines
1.9 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Miodrag Milanovic <mmicko@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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#
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# Tech data:
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# https://tang.sipeed.com/en/hardware-overview/lichee-tang/
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#
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# Board diagram/pinout:
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# https://tang.sipeed.com/hardware-overview/lichee-tang/images/newtang_pinout.png
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# https://tang.sipeed.com/hardware-overview/lichee-tang/images/E203_pin.png
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from migen import *
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from litex.build.generic_platform import *
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from litex.build.anlogic.platform import AnlogicPlatform
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from litex.build.openfpgaloader import OpenFPGALoader
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk24", 0, Pins("K14"), IOStandard("LVCMOS33")),
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# RGB LED
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("user_led", 0, Pins("R3"), IOStandard("LVCMOS33")), # R
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("user_led", 1, Pins("J14"), IOStandard("LVCMOS33")), # G
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("user_led", 2, Pins("P13"), IOStandard("LVCMOS33")), # B
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# Buttons.
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("user_btn", 0, Pins("K16"), IOStandard("LVCMOS33")), # USER_KEY
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# Serial
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("serial", 0,
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Subsignal("tx", Pins("J13")),
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Subsignal("rx", Pins("H13")),
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IOStandard("LVCMOS33")
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = []
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# Platform -----------------------------------------------------------------------------------------
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class Platform(AnlogicPlatform):
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default_clk_name = "clk24"
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default_clk_period = 1e9/24e6
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def __init__(self, toolchain="td"):
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AnlogicPlatform.__init__(self, "EG4S20BG256", _io, _connectors, toolchain=toolchain)
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def create_programmer(self):
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return OpenFPGALoader("licheeTang")
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def do_finalize(self, fragment):
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AnlogicPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk24", loose=True), 1e9/24e6)
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