113 lines
4.2 KiB
Python
Executable File
113 lines
4.2 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2024 Gwenhael Goavec-merou<gwenhael.goavec-merou@trabucayre.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from litex.gen import *
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from litex_boards.platforms import olimex_gatemate_a1_evb
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from litex.build.io import CRG
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from litex.soc.cores.clock.colognechip import GateMatePLL
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.build.generic_platform import Pins
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.video import VideoVGAPHY
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq, with_video_terminal):
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self.rst = Signal()
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rst_n = Signal()
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self.cd_sys = ClockDomain()
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if with_video_terminal:
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self.cd_vga = ClockDomain()
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# # #
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# Clk / Rst
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clk0 = platform.request("clk0")
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self.rst = ~platform.request("user_btn_n", 0)
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self.specials += Instance("CC_USR_RSTN", o_USR_RSTN = rst_n)
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# PLL
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self.pll = pll = GateMatePLL(perf_mode="economy")
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self.comb += pll.reset.eq(~rst_n | self.rst)
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pll.register_clkin(clk0, 10e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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if with_video_terminal:
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self.pll_video = pll_video = GateMatePLL(perf_mode="economy")
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self.comb += pll_video.reset.eq(~rst_n | self.rst)
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pll_video.register_clkin(clk0, 10e6)
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pll_video.create_clkout(self.cd_vga, 65e6)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=24e6,
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with_video_terminal = False,
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with_led_chaser = True,
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**kwargs):
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platform = olimex_gatemate_a1_evb.Platform()
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# CRG --------------------------------------------------------------------------------------
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self.crg = _CRG(platform, sys_clk_freq, with_video_terminal)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on GateMate EVB", **kwargs)
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# Video Terminal ---------------------------------------------------------------------------
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if with_video_terminal:
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vga_pads = platform.request("vga")
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self.videophy = VideoVGAPHY(vga_pads, clock_domain="vga")
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self.add_video_terminal(phy=self.videophy, timings="1024x768@60Hz", clock_domain="vga")
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#self.add_video_colorbars(phy=self.videophy, timings="1024x768@60Hz", clock_domain="vga")
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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pads = platform.request_all("user_led_n"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=olimex_gatemate_a1_evb.Platform, description="LiteX SoC on Olimex Gatemate A1 EVB")
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parser.add_target_argument("--sys-clk-freq", default=24e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA).")
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parser.add_target_argument("--flash", action="store_true", help="Flash bitstream.")
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = args.sys_clk_freq,
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with_video_terminal = args.with_video_terminal,
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**parser.soc_argdict)
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if args.flash:
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prog = soc.platform.create_programmer()
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prog.flash(0, builder.get_bitstream_filename(mode="flash"))
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if __name__ == "__main__":
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main()
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