180 lines
7.1 KiB
Python
Executable File
180 lines
7.1 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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# Build/Use ----------------------------------------------------------------------------------------
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# Build/Load bitstream:
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# ./siglent_sds1104xe.py --with-etherbone --uart-name=crossover --csr-csv=csr.csv --build --load
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#
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# Test Ethernet:
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# ping 192.168.1.50
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#
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# Test Console:
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# litex_server --udp
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# litex_term crossover
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#
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#
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# With Jtagbone ------------------------------------------------------------------------------------
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# Build/Load bitstream:
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# ./siglent_sds1104xe.py --with-jtagbone --uart-name=crossover --csr-csv=csr.csv --build --load
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#
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# In a first terminal:
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# litex_server --jtag --jtag-config openocd_xc7z_ft232.cfg
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#
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# In a second terminal:
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# litex_cli --regs # to dump all registers
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# Or
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# litex_term crossover # to have access to LiteX bios
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#
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# --------------------------------------------------------------------------------------------------
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from migen import *
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from litex.gen import *
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from litex_boards.platforms import siglent_sds1104xe
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.video import VideoVGAPHY
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from litedram.common import PHYPadsReducer
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from litedram.modules import MT41K64M16
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from litedram.phy import s7ddrphy
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from liteeth.phy.mii import LiteEthPHYMII
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq, with_ethernet=False):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_sys4x = ClockDomain()
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self.cd_sys4x_dqs = ClockDomain()
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self.cd_idelay = ClockDomain()
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self.cd_dvi = ClockDomain()
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# # #
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# Clk / Rst
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clk25 = ClockSignal("eth_tx") if with_ethernet else platform.request("eth_clocks").rx
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# PLL
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self.pll = pll = S7PLL(speedgrade=-1)
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pll.register_clkin(clk25, 25e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_idelay, 200e6)
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pll.create_clkout(self.cd_dvi, 33.3e6)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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self.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=100e6,
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with_etherbone = True,
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eth_ip = "192.168.1.50",
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with_video_terminal = False,
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with_video_framebuffer = False,
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**kwargs):
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platform = siglent_sds1104xe.Platform()
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# CRG --------------------------------------------------------------------------------------
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self.crg = _CRG(platform, sys_clk_freq, with_ethernet=with_etherbone)
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# SoCCore ----------------------------------------------------------------------------------
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if kwargs.get("uart_name", "serial") == "serial":
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kwargs["uart_name"] = "crossover" # Defaults to Crossover UART.
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Siglent SDS1104X-E", **kwargs)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.ddrphy = s7ddrphy.A7DDRPHY(
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pads = PHYPadsReducer(platform.request("ddram"), [0, 1, 2, 3]),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT41K64M16(sys_clk_freq, "1:4"),
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# Etherbone + Ethernet ---------------------------------------------------------------------
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if with_etherbone:
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# Ethernet PHY
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self.ethphy = LiteEthPHYMII(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"),
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)
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# Etherbone.
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self.add_etherbone(
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phy = self.ethphy,
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ip_address = "192.168.1.50",
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mac_address = 0x10e2d5000000,
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data_width = 8,
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with_ethmac = True,
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)
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# Video ------------------------------------------------------------------------------------
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video_timings = ("800x480@60Hz", {
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"pix_clk" : 33.3e6,
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"h_active" : 800,
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"h_blanking" : 256,
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"h_sync_offset" : 210,
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"h_sync_width" : 1,
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"v_active" : 480,
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"v_blanking" : 45,
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"v_sync_offset" : 22,
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"v_sync_width" : 1,
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})
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if with_video_terminal or with_video_framebuffer:
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self.videophy = VideoVGAPHY(platform.request("lcd"), clock_domain="dvi")
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if with_video_terminal:
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self.add_video_terminal(phy=self.videophy, timings=video_timings, clock_domain="dvi")
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if with_video_framebuffer:
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self.add_video_framebuffer(phy=self.videophy, timings=video_timings, clock_domain="dvi")
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=siglent_sds1104xe.Platform, description="LiteX SoC on SDS1104X-E.")
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parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
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parser.add_target_argument("--eth-ip", default="192.168.1.50", help="Ethernet/Etherbone IP address.")
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viopts = parser.target_group.add_mutually_exclusive_group()
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viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
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viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI).")
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = args.sys_clk_freq,
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with_etherbone = args.with_etherbone,
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eth_ip = args.eth_ip,
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with_video_terminal = args.with_video_terminal,
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with_video_framebuffer = args.with_video_framebuffer,
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**parser.soc_argdict
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)
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"), device=1)
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if __name__ == "__main__":
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main()
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