214 lines
9.4 KiB
Python
Executable File
214 lines
9.4 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2023 Gabriel Somlo <gsomlo@gmail.com>
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# Copyright (c) 2022 Andrew Gillham <gillham@roadsign.com>
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# Copyright (c) 2014-2015 Sebastien Bourdeauducq <sb@m-labs.hk>
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# Copyright (c) 2014-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2014-2015 Yann Sionneau <ys@m-labs.hk>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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from migen import *
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from litex.gen import *
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from litex_boards.platforms import sitlinv_stlv7325_v2
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.bitbang import I2CMaster
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from litex.soc.cores.video import VideoS7HDMIPHY
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from litedram.modules import MT8JTF12864
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from litedram.phy import s7ddrphy
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from liteeth.phy.s7rgmii import LiteEthPHYRGMII
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from litepcie.phy.s7pciephy import S7PCIEPHY
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from litepcie.software import generate_litepcie_software
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_sys4x = ClockDomain()
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self.cd_idelay = ClockDomain()
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self.cd_hdmi = ClockDomain()
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self.cd_hdmi5x = ClockDomain()
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# # #
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# Clk/Rst.
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clk200 = platform.request("clk200")
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clk50 = platform.request("clk50")
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rst_n = platform.request("cpu_reset_n")
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# PLL.
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self.pll = pll = S7PLL(speedgrade=-2)
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self.comb += pll.reset.eq(~rst_n | self.rst)
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pll.register_clkin(clk200, 200e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_idelay, 200e6)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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self.submodules.pll2 = pll2 = S7PLL(speedgrade=-2)
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self.comb += pll2.reset.eq(~rst_n | self.rst)
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pll2.register_clkin(clk50, 50e6)
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pll2.create_clkout(self.cd_hdmi, 25e6, margin=0)
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pll2.create_clkout(self.cd_hdmi5x, 125e6, margin=0)
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self.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=100e6,
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vccio = "3.3V",
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with_ethernet = False,
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with_led_chaser = True,
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with_pcie = False,
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with_sata = False, sata_gen="gen2",
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with_video_colorbars = False,
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with_video_framebuffer = False,
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with_video_terminal = False,
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**kwargs):
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platform = sitlinv_stlv7325_v2.Platform(vccio)
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# CRG --------------------------------------------------------------------------------------
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self.crg = _CRG(platform, sys_clk_freq)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Sitlinv STLV7325-v2", **kwargs)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq,
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)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT8JTF12864(sys_clk_freq, "1:4"),
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l2_cache_size = kwargs.get("l2_size", 8192),
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)
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# Ethernet / Etherbone ---------------------------------------------------------------------
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if with_ethernet:
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self.ethphy = LiteEthPHYRGMII(
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clock_pads = self.platform.request("eth_clocks", 0),
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pads = self.platform.request("eth", 0),
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tx_delay = 1.417e-9,
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rx_delay = 1.417e-9,
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)
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self.add_ethernet(phy=self.ethphy)
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# PCIe -------------------------------------------------------------------------------------
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if with_pcie:
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self.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
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data_width = 128,
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bar0_size = 0x20000)
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self.add_pcie(phy=self.pcie_phy, ndmas=1)
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# TODO verify / test
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# SATA -------------------------------------------------------------------------------------
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if with_sata:
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from litex.build.generic_platform import Subsignal, Pins
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from litesata.phy import LiteSATAPHY
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# RefClk, Generate 150MHz from PLL.
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self.cd_sata_refclk = ClockDomain()
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self.crg.pll.create_clkout(self.cd_sata_refclk, 150e6)
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sata_refclk = ClockSignal("sata_refclk")
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platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-52]")
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# PHY
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self.sata_phy = LiteSATAPHY(platform.device,
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refclk = sata_refclk,
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pads = platform.request("sata", 0),
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gen = sata_gen,
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clk_freq = sys_clk_freq,
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data_width = 16)
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# Core
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self.add_sata(phy=self.sata_phy, mode="read+write")
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# HDMI Options -----------------------------------------------------------------------------
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if (with_video_colorbars or with_video_framebuffer or with_video_terminal):
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self.submodules.videophy = VideoS7HDMIPHY(platform.request("hdmi_out"), clock_domain="hdmi")
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if with_video_colorbars:
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self.add_video_colorbars(phy=self.videophy, timings="640x480@60Hz", clock_domain="hdmi")
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if with_video_terminal:
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self.add_video_terminal(phy=self.videophy, timings="640x480@60Hz", clock_domain="hdmi")
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if with_video_framebuffer:
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self.add_video_framebuffer(phy=self.videophy, timings="640x480@60Hz", clock_domain="hdmi")
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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pads = platform.request_all("user_led_n"),
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sys_clk_freq = sys_clk_freq)
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# I2C --------------------------------------------------------------------------------------
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self.i2c = I2CMaster(platform.request("i2c"))
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=sitlinv_stlv7325_v2.Platform, description="LiteX SoC on AliExpress STLV7325-v2.")
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parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--vccio", default="3.3V", type=str, help="IO Voltage (set by J4), can be 2.5V or 3.3V")
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parser.add_target_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
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parser.add_target_argument("--driver", action="store_true", help="Generate PCIe driver.")
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parser.add_target_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
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parser.add_target_argument("--with-sata", action="store_true", help="Enable SATA support.")
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parser.add_target_argument("--sata-gen", default="2", help="SATA Gen..", choices=["1", "2", "3"])
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sdopts = parser.target_group.add_mutually_exclusive_group()
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sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
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sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
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viopts = parser.target_group.add_mutually_exclusive_group()
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viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
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viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI).")
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viopts.add_argument("--with-video-colorbars", action="store_true", help="Enable Video Colorbars (HDMI).")
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = args.sys_clk_freq,
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vccio = args.vccio,
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with_ethernet = args.with_ethernet,
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with_pcie = args.with_pcie,
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with_sata = args.with_sata,
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sata_gen = "gen" + args.sata_gen,
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with_video_colorbars = args.with_video_colorbars,
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with_video_framebuffer = args.with_video_framebuffer,
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with_video_terminal = args.with_video_terminal,
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**parser.soc_argdict
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)
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if args.with_spi_sdcard:
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soc.add_spi_sdcard()
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if args.with_sdcard:
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soc.add_sdcard()
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.driver:
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generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver"))
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if __name__ == "__main__":
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main()
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