143 lines
5.8 KiB
Python
Executable File
143 lines
5.8 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2023 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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import litex_boards.platforms.antmicro_sdi_mipi_video_converter
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from litex.soc.cores.ram import NXLRAM
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from litex.soc.cores.clock import NXPLL
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from litex.build.io import CRG
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from litex.build.generic_platform import *
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.build.lattice.oxide import oxide_args, oxide_argdict
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from litex.build.lattice.radiant import radiant_build_argdict, radiant_build_args
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kB = 1024
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mB = 1024*kB
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_por = ClockDomain()
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self.clock_domains.cd_sys = ClockDomain()
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# Built in OSC
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self.submodules.hf_clk = NXOSCA()
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hf_clk_freq = 25e6
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self.hf_clk.create_hf_clk(self.cd_por, hf_clk_freq)
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# Power on reset
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por_count = Signal(16, reset=2**16-1)
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por_done = Signal()
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self.comb += por_done.eq(por_count == 0)
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self.sync.por += If(~por_done, por_count.eq(por_count - 1))
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# PLL
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self.submodules.sys_pll = sys_pll = NXPLL(platform=platform, create_output_port_clocks=True)
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sys_pll.register_clkin(self.cd_por.clk, hf_clk_freq)
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sys_pll.create_clkout(self.cd_sys, sys_clk_freq)
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self.specials += AsyncResetSynchronizer(self.cd_sys, ~self.sys_pll.locked | ~por_done )
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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mem_map = {
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"rom" : 0x00000000,
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"sram" : 0x40000000,
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"main_ram": 0x60000000,
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"csr" : 0xf0000000,
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}
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def __init__(self, sys_clk_freq=int(75e6), device="LIFCL-40-9BG256C", toolchain="radiant", with_led_chaser=True, **kwargs):
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platform = litex_boards.platforms.antmicro_sdi_mipi_video_converter.Platform(device=device, toolchain=toolchain)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# SoCCore -----------------------------------------_----------------------------------------
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# Disable Integrated SRAM since we want to instantiate LRAM specifically for it
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kwargs["integrated_sram_size"] = 0
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Crosslink-NX Evaluation Board", **kwargs)
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# 128KB LRAM (used as SRAM) ---------------------------------------------------------------
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self.submodules.spram = NXLRAM(32, 64*kB)
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self.bus.add_slave("sram", self.spram.bus, SoCRegion(origin=self.mem_map["sram"], size=16*kB))
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self.submodules.main_ram = NXLRAM(32, 64*kB)
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self.bus.add_slave("main_ram", self.main_ram.bus, SoCRegion(origin=self.mem_map["main_ram"], size=64*kB))
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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pads = Cat(*[platform.request("user_led", i) for i in range(2)]),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.soc.integration.soc import LiteXSoCArgumentParser
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parser = LiteXSoCArgumentParser(description="LiteX SoC on Crosslink-NX Eval Board")
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target_group = parser.add_argument_group(title="Target options")
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target_group.add_argument("--build", action="store_true", help="Build design.")
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target_group.add_argument("--load", action="store_true", help="Load bitstream.")
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target_group.add_argument("--toolchain", default="radiant", help="FPGA toolchain (radiant or prjoxide).")
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target_group.add_argument("--device", default="LIFCL-40-9BG256C", help="FPGA device (LIFCL-40-9BG400C, LIFCL-40-8BG400CES, or LIFCL-40-8BG400CES2).")
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target_group.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
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target_group.add_argument("--programmer", default="radiant", help="Programmer (radiant or ecpprog).")
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target_group.add_argument("--prog-target", default="direct", help="Programming Target (direct or flash).")
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builder_args(parser)
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soc_core_args(parser)
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oxide_args(parser)
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radiant_build_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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device = args.device,
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toolchain = args.toolchain,
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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builder_kargs = oxide_argdict(args) if args.toolchain == "oxide" else radiant_build_argdict(args)
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if args.build:
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builder.build(**builder_kargs)
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if args.load:
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prog = soc.platform.create_programmer(args.prog_target, args.programmer)
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if args.programmer == "ecpprog" and args.prog_target == "flash":
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prog.flash(address=args.address, bitstream=builder.get_bitstream_filename(mode="sram"))
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else:
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if args.programmer == "radiant":
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os.system("sudo modprobe -rf ftdi_sio")
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if args.programmer == "radiant":
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os.system("sudo modprobe ftdi_sio")
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if __name__ == "__main__":
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main()
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