Gwenhael Goavec-Merou 3050716e8e boards: digilent_nexys4ddr, kosagi_netv2, sipeed_tang_primer_20k: added eth_ip/remote_ip arg		2024-09-13 15:40:12 +02:00
..
platforms	platforms/sqrl_xcu1525: Revert previous commit, clk constraints were already present in DDR4 constraints.	2024-09-13 09:45:24 +02:00
prog	xilinx_zc706: new Xilinx/AMD Zynq7000 based board	2024-03-26 20:49:54 +01:00
targets	boards: digilent_nexys4ddr, kosagi_netv2, sipeed_tang_primer_20k: added eth_ip/remote_ip arg	2024-09-13 15:40:12 +02:00
__init__.py	litex_boards: Remove short imports since not really longer useful and mess up Python imports.	2022-05-03 17:53:57 +02:00