diff --git a/litex/soc/cores/cpu/cv32e40p/core.py b/litex/soc/cores/cpu/cv32e40p/core.py
index 9fbaf93d5..79dfbeb1d 100644
--- a/litex/soc/cores/cpu/cv32e40p/core.py
+++ b/litex/soc/cores/cpu/cv32e40p/core.py
@@ -186,7 +186,7 @@ class Wishbone2APB(LiteXModule):
 
 class TraceCollector(LiteXModule):
     def __init__(self, trace_depth=16384):
-        self.bus  = bus  = wishbone.Interface()
+        self.bus  = bus  = wishbone.Interface(data_width=32, address_width=32, addressing="word")
         self.sink = sink = stream.Endpoint([("data", 32)])
 
         clear   = Signal()
diff --git a/litex/soc/cores/emif.py b/litex/soc/cores/emif.py
index 0332dac52..923a30e99 100644
--- a/litex/soc/cores/emif.py
+++ b/litex/soc/cores/emif.py
@@ -18,7 +18,7 @@ class EMIF(LiteXModule):
     Provides a simple EMIF to Wishbone Master bridge.
     """
     def __init__(self, pads):
-        self.bus = bus = wishbone.Interface()
+        self.bus = bus = wishbone.Interface(data_width=32, address_width=32, addressing="word")
 
         # # #
 
@@ -87,7 +87,7 @@ class EMIF(LiteXModule):
 
 class EMIF16To32Adapter(LiteXModule):
     def __init__(self, emif):
-        self.bus = bus = wishbone.Interface()
+        self.bus = bus = wishbone.Interface(data_width=32, address_width=32, addressing="word")
 
         # # #
 
diff --git a/litex/soc/cores/hyperbus.py b/litex/soc/cores/hyperbus.py
index f6c743c4e..da8c03d2b 100644
--- a/litex/soc/cores/hyperbus.py
+++ b/litex/soc/cores/hyperbus.py
@@ -29,7 +29,7 @@ class HyperRAM(LiteXModule):
     """
     def __init__(self, pads, latency=6, sys_clk_freq=None):
         self.pads = pads
-        self.bus  = bus = wishbone.Interface()
+        self.bus  = bus = wishbone.Interface(data_width=32, address_width=32, addressing="word")
 
         # # #
 
diff --git a/litex/soc/cores/i2s.py b/litex/soc/cores/i2s.py
index 1113dcc87..d3d7d1ba4 100644
--- a/litex/soc/cores/i2s.py
+++ b/litex/soc/cores/i2s.py
@@ -163,7 +163,7 @@ class S7I2S(LiteXModule):
         self.comb += [rising_edge.eq(clk_pin & ~clk_d), falling_edge.eq(~clk_pin & clk_d)]
 
         # Wishbone bus
-        self.bus = bus = wishbone.Interface()
+        self.bus = bus = wishbone.Interface(data_width=32, address_width=32, addressing="word")
         rd_ack = Signal()
         wr_ack = Signal()
         self.comb += [
diff --git a/litex/soc/cores/led.py b/litex/soc/cores/led.py
index 7ac782d4c..477b93e04 100644
--- a/litex/soc/cores/led.py
+++ b/litex/soc/cores/led.py
@@ -134,7 +134,7 @@ class WS2812(LiteXModule):
     """
     def __init__(self, pad, nleds, sys_clk_freq, bus_mastering=False, bus_base=None, revision="new", init=None):
         if bus_mastering:
-            self.bus  = bus = wishbone.Interface(data_width=32)
+            self.bus  = bus = wishbone.Interface(data_width=32, address_width=32, addressing="word")
         else:
             # Memory.
             mem = Memory(32, nleds, init=init)
@@ -145,7 +145,7 @@ class WS2812(LiteXModule):
             self.wb_mem = wishbone.SRAM(
                 mem_or_size = mem,
                 read_only   = False,
-                bus         = wishbone.Interface(data_width=32)
+                bus         = wishbone.Interface(data_width=32, address_width=32, addressing="word")
             )
             self.bus = self.wb_mem.bus
 
diff --git a/litex/soc/cores/ram/lattice_ice40.py b/litex/soc/cores/ram/lattice_ice40.py
index 08ea05967..c1894cf60 100644
--- a/litex/soc/cores/ram/lattice_ice40.py
+++ b/litex/soc/cores/ram/lattice_ice40.py
@@ -27,7 +27,7 @@ of 4 SPRAMs for this, so the only other valid config is using all 4 SPRAMs by de
 
 class Up5kSPRAM(LiteXModule):
     def __init__(self, width=32, size=64*kB):
-        self.bus = wishbone.Interface(width)
+        self.bus = wishbone.Interface(data_width=width, address_width=32, addressing="word")
 
         # # #
 
diff --git a/litex/soc/cores/ram/lattice_nx.py b/litex/soc/cores/ram/lattice_nx.py
index 836c1a314..b2fa75fee 100644
--- a/litex/soc/cores/ram/lattice_nx.py
+++ b/litex/soc/cores/ram/lattice_nx.py
@@ -53,7 +53,7 @@ def initval_parameters(contents, width):
 
 class NXLRAM(LiteXModule):
     def __init__(self, width=32, size=128*kB, init=[]):
-        self.bus = wishbone.Interface(width)
+        self.bus = wishbone.Interface(data_width=width, address_width=32, addressing="word")
         assert width in [32, 64]
         self.width = width
         self.size = size
diff --git a/litex/soc/cores/spi/spi_bone.py b/litex/soc/cores/spi/spi_bone.py
index e0df08e20..c85aa7b34 100644
--- a/litex/soc/cores/spi/spi_bone.py
+++ b/litex/soc/cores/spi/spi_bone.py
@@ -133,7 +133,7 @@ class SPIBone(LiteXModule, ModuleDoc):
     The bridge core is designed to run at 1/4 the system clock.
     """
     def __init__(self, pads, wires=4, with_tristate=True):
-        self.bus = bus = wishbone.Interface(address_width=32, data_width=32)
+        self.bus = bus = wishbone.Interface(address_width=32, data_width=32, addressing="word")
 
         # # #
 
diff --git a/litex/soc/cores/spi/spi_mmap.py b/litex/soc/cores/spi/spi_mmap.py
index 7ef213137..39c55c487 100644
--- a/litex/soc/cores/spi/spi_mmap.py
+++ b/litex/soc/cores/spi/spi_mmap.py
@@ -361,7 +361,7 @@ class SPICtrl(LiteXModule):
 
 class SPITXMMAP(LiteXModule):
     def __init__(self, ctrl, data_width=32, nslots=1, origin=0x0000_0000):
-        self.bus    = bus    = wishbone.Interface(data_width=data_width)
+        self.bus    = bus    = wishbone.Interface(data_width=data_width, address_width=32, addressing="word")
         self.source = source = stream.Endpoint(spi_layout(
             data_width = data_width,
             be_width   = data_width//8,
@@ -429,7 +429,7 @@ class SPITXMMAP(LiteXModule):
 
 class SPIRXMMAP(LiteXModule):
     def __init__(self, ctrl, data_width=32, nslots=1, origin=0x0000_0000):
-        self.bus  = bus  = wishbone.Interface(data_width=data_width)
+        self.bus  = bus  = wishbone.Interface(data_width=data_width, address_width=32, addressing="word")
         self.sink = sink = stream.Endpoint(spi_layout(
             data_width = data_width,
             be_width   = data_width//8,
diff --git a/litex/soc/cores/spi_opi.py b/litex/soc/cores/spi_opi.py
index 851a99fac..0e1f68d31 100644
--- a/litex/soc/cores/spi_opi.py
+++ b/litex/soc/cores/spi_opi.py
@@ -435,7 +435,7 @@ class S7SPIOPI(LiteXModule):
              bit of additional logic and pipelining, we can aggregate data into 32-bit words going into a
              32-bit FIFO_SYNC_MACRO, which is what we do in this implementation.
         """)
-        self.bus = bus = wishbone.Interface()
+        self.bus = bus = wishbone.Interface(data_width=32, address_width=32, addressing="word")
 
         self.command = CSRStorage(description="Write individual bits to issue special commands to SPI; setting multiple bits at once leads to undefined behavior.",
             fields=[
diff --git a/litex/soc/cores/uart.py b/litex/soc/cores/uart.py
index 723337897..12ca5593f 100644
--- a/litex/soc/cores/uart.py
+++ b/litex/soc/cores/uart.py
@@ -310,7 +310,7 @@ class Stream2Wishbone(LiteXModule):
     def __init__(self, phy=None, clk_freq=None, data_width=32, address_width=32):
         self.sink     = sink   = stream.Endpoint([("data", 8)]) if phy is None else phy.source
         self.source   = source = stream.Endpoint([("data", 8)]) if phy is None else phy.sink
-        self.wishbone = wishbone.Interface(data_width=data_width, adr_width=address_width)
+        self.wishbone = wishbone.Interface(data_width=data_width, address_width=address_width, addressing="word")
 
         # # #
         assert data_width    in [8, 16, 32]
diff --git a/litex/soc/cores/usb_ohci.py b/litex/soc/cores/usb_ohci.py
index 2ca50daac..264eac726 100644
--- a/litex/soc/cores/usb_ohci.py
+++ b/litex/soc/cores/usb_ohci.py
@@ -26,8 +26,8 @@ class USBOHCI(LiteXModule):
         self.usb_clk_freq   = int(usb_clk_freq)
         self.dma_data_width = dma_data_width
 
-        self.wb_ctrl = wb_ctrl = wishbone.Interface(data_width=32)
-        self.wb_dma  = wb_dma  = wishbone.Interface(data_width=dma_data_width)
+        self.wb_ctrl = wb_ctrl = wishbone.Interface(data_width=32,             address_width=32, addressing="word")
+        self.wb_dma  = wb_dma  = wishbone.Interface(data_width=dma_data_width, address_width=32, addressing="word")
 
         self.interrupt = Signal()
 
diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 6c2a0a652..3fd236338 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -1627,7 +1627,9 @@ class LiteXSoC(SoC):
                     else:
                         mem_wb  = wishbone.Interface(
                             data_width = self.cpu.mem_axi.data_width,
-                            adr_width  = 32-log2_int(mem_bus.data_width//8))
+                            adr_width  = 32-log2_int(mem_bus.data_width//8,
+                            addressing = "word",
+                        ))
                         mem_a2w = axi.AXI2Wishbone(
                             axi          = mem_bus,
                             wishbone     = mem_wb,
@@ -1664,7 +1666,7 @@ class LiteXSoC(SoC):
             port.data_width = 2**int(log2(port.data_width)) # Round to nearest power of 2.
 
             # Create Wishbone Slave.
-            wb_sdram = wishbone.Interface(data_width=self.bus.data_width)
+            wb_sdram = wishbone.Interface(data_width=self.bus.data_width, address_width=32, addressing="word")
             self.bus.add_slave(name="main_ram", slave=wb_sdram)
 
             # L2 Cache
@@ -1676,7 +1678,7 @@ class LiteXSoC(SoC):
                 l2_cache = wishbone.Cache(
                     cachesize = l2_cache_size//4,
                     master    = wb_sdram,
-                    slave     = wishbone.Interface(l2_cache_data_width),
+                    slave     = wishbone.Interface(data_width=l2_cache_data_width, address_width=32, addressing="word"),
                     reverse   = l2_cache_reverse)
                 if l2_cache_full_memory_we:
                     l2_cache = FullMemoryWE()(l2_cache)
@@ -1684,7 +1686,7 @@ class LiteXSoC(SoC):
                 litedram_wb = self.l2_cache.slave
                 self.add_config("L2_SIZE", l2_cache_size)
             else:
-                litedram_wb = wishbone.Interface(port.data_width)
+                litedram_wb = wishbone.Interface(data_width=port.data_width, address_width=32, addressing="word")
                 self.submodules += wishbone.Converter(wb_sdram, litedram_wb)
 
             # Wishbone Slave <--> LiteDRAM bridge.
@@ -1926,7 +1928,11 @@ class LiteXSoC(SoC):
         # Block2Mem DMA.
         if "read" in mode:
             self.check_if_exists(f"{name}_block2mem")
-            bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.get_address_width(standard="wishbone"))
+            bus = wishbone.Interface(
+                data_width = self.bus.data_width,
+                adr_width  = self.bus.get_address_width(standard="wishbone"),
+                addressing = "word",
+            )
             sdcard_block2mem = SDBlock2MemDMA(bus=bus, endianness=self.cpu.endianness)
             self.add_module(name=f"{name}_block2mem", module=sdcard_block2mem)
             self.comb += sdcard_core.source.connect(sdcard_block2mem.sink)
@@ -1936,7 +1942,11 @@ class LiteXSoC(SoC):
         # Mem2Block DMA.
         if "write" in mode:
             self.check_if_exists(f"{name}_mem2block")
-            bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.get_address_width(standard="wishbone"))
+            bus = wishbone.Interface(
+                data_width = self.bus.data_width,
+                adr_width  = self.bus.get_address_width(standard="wishbone"),
+                addressing = "word",
+            )
             sdcard_mem2block = SDMem2BlockDMA(bus=bus, endianness=self.cpu.endianness)
             self.add_module(name=f"{name}_mem2block", module=sdcard_mem2block)
             self.comb += sdcard_mem2block.source.connect(sdcard_core.sink)
@@ -2007,11 +2017,16 @@ class LiteXSoC(SoC):
         # Sector2Mem DMA.
         if "read" in mode:
             self.check_if_exists(f"{name}_sector2mem")
-            bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.get_address_width(standard="wishbone"))
+            bus = wishbone.Interface(
+                data_width = self.bus.data_width,
+                adr_width  = self.bus.get_address_width(standard="wishbone"),
+                addressing = "word",
+            )
             sata_sector2mem = LiteSATASector2MemDMA(
                port       = sata_crossbar.get_port(),
                bus        = bus,
-               endianness = self.cpu.endianness)
+               endianness = self.cpu.endianness,
+            )
             self.add_module(name=f"{name}_sector2mem", module=sata_sector2mem)
             dma_bus = getattr(self, "dma_bus", self.bus)
             dma_bus.add_master(name=f"{name}_sector2mem", master=bus)
@@ -2019,11 +2034,16 @@ class LiteXSoC(SoC):
         # Mem2Sector DMA.
         if "write" in mode:
             self.check_if_exists(f"{name}_mem2sector")
-            bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.get_address_width(standard="wishbone"))
+            bus = wishbone.Interface(
+                data_width = self.bus.data_width,
+                adr_width  = self.bus.get_address_width(standard="wishbone"),
+                addressing = "word",
+            )
             sata_mem2sector = LiteSATAMem2SectorDMA(
                bus        = bus,
                port       = sata_crossbar.get_port(),
-               endianness = self.cpu.endianness)
+               endianness = self.cpu.endianness,
+            )
             self.add_module(name=f"{name}_mem2sector", module=sata_mem2sector)
             dma_bus = getattr(self, "dma_bus", self.bus)
             dma_bus.add_master(name=f"{name}_mem2sector", master=bus)
diff --git a/litex/soc/interconnect/avalon/avalon_mm_to_wishbone.py b/litex/soc/interconnect/avalon/avalon_mm_to_wishbone.py
index 0e85f801a..ef742d83b 100644
--- a/litex/soc/interconnect/avalon/avalon_mm_to_wishbone.py
+++ b/litex/soc/interconnect/avalon/avalon_mm_to_wishbone.py
@@ -17,7 +17,7 @@ from litex.soc.interconnect.avalon import AvalonMMInterface
 class AvalonMM2Wishbone(Module):
     def __init__(self, data_width=32, avalon_address_width=32, wishbone_address_width=32, wishbone_base_address=0x0, burst_increment=1, avoid_combinatorial_loop=False):
         self.a2w_avl = avl = AvalonMMInterface (data_width=data_width, adr_width=avalon_address_width)
-        self.a2w_wb  = wb  = wishbone.Interface(data_width=data_width, adr_width=wishbone_address_width, bursting=True)
+        self.a2w_wb  = wb  = wishbone.Interface(data_width=data_width, adr_width=wishbone_address_width, addressing="word", bursting=True)
 
         read_access   = Signal()
         readdatavalid = Signal()
diff --git a/litex/soc/interconnect/wishbone.py b/litex/soc/interconnect/wishbone.py
index 1bd05bbd7..e19d55939 100644
--- a/litex/soc/interconnect/wishbone.py
+++ b/litex/soc/interconnect/wishbone.py
@@ -67,7 +67,7 @@ class Interface(Record):
 
     @staticmethod
     def like(other):
-        return Interface(len(other.dat_w))
+        return Interface(data_width=other.data_width, address_width=other.address_width, addressing=other.addressing)
 
     def _do_transaction(self):
         yield self.cyc.eq(1)
@@ -395,7 +395,7 @@ class Converter(Module):
 class SRAM(Module):
     def __init__(self, mem_or_size, read_only=None, write_only=None, init=None, bus=None, name=None):
         if bus is None:
-            bus = Interface()
+            bus = Interface(data_width=32, address_width=32, addressing="word")
         assert bus.addressing == "word" # FIXME: Test/Remove byte addressing limitation.
         self.bus = bus
         bus_data_width = len(self.bus.dat_r)
diff --git a/litex/tools/litex_periph_gen.py b/litex/tools/litex_periph_gen.py
index 5e235ad21..177832c3a 100755
--- a/litex/tools/litex_periph_gen.py
+++ b/litex/tools/litex_periph_gen.py
@@ -76,8 +76,8 @@ class LiteXSoCGenerator(SoCMini):
 
         # MMAP Slave Interface ---------------------------------------------------------------------
         s_bus = {
-            "wishbone" : wishbone.Interface(),
-            "axi-lite" : axi.AXILiteInterface(),
+            "wishbone" : wishbone.Interface(data_width=32, address_width=32, addressing="word"),
+            "axi-lite" : axi.AXILiteInterface(data_width=32, address_width=32),
 
         }[kwargs["bus_standard"]]
         self.bus.add_master(name="mmap_s", master=s_bus)
@@ -88,8 +88,8 @@ class LiteXSoCGenerator(SoCMini):
         # MMAP Master Interface --------------------------------------------------------------------
         # FIXME: Allow Region configuration.
         m_bus = {
-            "wishbone" : wishbone.Interface(),
-            "axi-lite" : axi.AXILiteInterface(),
+            "wishbone" : wishbone.Interface(data_width=32, address_width=32, addressing="word"),
+            "axi-lite" : axi.AXILiteInterface(data_width=32, address_width=32),
 
         }[kwargs["bus_standard"]]
         wb_region = SoCRegion(origin=0x2000_0000, size=0x1000_0000, cached=True) # FIXME.
diff --git a/test/test_axi.py b/test/test_axi.py
index 4771aa791..fd2dae570 100644
--- a/test/test_axi.py
+++ b/test/test_axi.py
@@ -248,7 +248,7 @@ class TestAXI(unittest.TestCase):
         class DUT(Module):
             def __init__(self):
                 self.axi      = AXIInterface(data_width=32, address_width=32, id_width=8)
-                self.wishbone = wishbone.Interface(data_width=32, adr_width=30)
+                self.wishbone = wishbone.Interface(data_width=32, adr_width=30, addressing="word")
 
                 axi2wishbone = AXI2Wishbone(self.axi, self.wishbone)
                 self.submodules += axi2wishbone
@@ -343,7 +343,7 @@ class TestAXI(unittest.TestCase):
             def __init__(self, dw_from=64, dw_to=32):
                 self.axi_master = AXIInterface(data_width=dw_from)
                 axi_slave       = AXIInterface(data_width=dw_to)
-                wb_slave        = wishbone.Interface(data_width=dw_to, address_width=axi_slave.address_width)
+                wb_slave        = wishbone.Interface(data_width=dw_to, address_width=axi_slave.address_width, addressing="word")
                 self.converter = AXIConverter(self.axi_master, axi_slave)
                 self.axi2wb    = AXI2Wishbone(axi_slave, wb_slave)
                 self.mem       = wishbone.SRAM(1024, bus=wb_slave, init=range(256))
diff --git a/test/test_axi_lite.py b/test/test_axi_lite.py
index 49548d055..3a5c819e5 100644
--- a/test/test_axi_lite.py
+++ b/test/test_axi_lite.py
@@ -149,13 +149,20 @@ class TestAXILite(unittest.TestCase):
     def test_wishbone2axilite2wishbone(self, data_width=32, address_width=32):
         class DUT(Module):
             def __init__(self):
-                self.wishbone = wishbone.Interface(data_width=data_width,
-                                                   adr_width=address_width - log2_int(data_width // 8))
+                self.wishbone = wishbone.Interface(
+                    data_width = data_width,
+                    adr_width  = address_width - log2_int(data_width // 8),
+                    addressing = "word",
+                )
 
                 # # #
 
                 axi_lite = AXILiteInterface(data_width=data_width, address_width=address_width)
-                wb  = wishbone.Interface(data_width=data_width, adr_width=address_width - log2_int(data_width // 8))
+                wb  = wishbone.Interface(
+                    data_width = data_width,
+                    adr_width  = address_width - log2_int(data_width // 8),
+                    addressing = "word",
+                )
 
                 wishbone2axi = Wishbone2AXILite(self.wishbone, axi_lite)
                 axi2wishbone = AXILite2Wishbone(axi_lite, wb)
diff --git a/test/test_wishbone.py b/test/test_wishbone.py
index ed91dced6..c9a71f66e 100644
--- a/test/test_wishbone.py
+++ b/test/test_wishbone.py
@@ -26,8 +26,8 @@ class TestWishbone(unittest.TestCase):
 
         class DUT(Module):
             def __init__(self):
-                self.wb16 = wishbone.Interface(data_width=16)
-                wb32      = wishbone.Interface(data_width=32)
+                self.wb16 = wishbone.Interface(data_width=16, address_width=32, addressing="word")
+                wb32      = wishbone.Interface(data_width=32, address_width=32, addressing="word")
                 up_converter = wishbone.UpConverter(self.wb16, wb32)
                 self.submodules += up_converter
                 wishbone_mem = wishbone.SRAM(32, bus=wb32)
@@ -45,9 +45,9 @@ class TestWishbone(unittest.TestCase):
 
         class DUT(Module):
             def __init__(self):
-                self.wb32 = wishbone.Interface(data_width=32)
-                wb64      = wishbone.Interface(data_width=64)
-                wb32      = wishbone.Interface(data_width=32)
+                self.wb32 = wishbone.Interface(data_width=32, address_width=32, addressing="word")
+                wb64      = wishbone.Interface(data_width=64, address_width=32, addressing="word")
+                wb32      = wishbone.Interface(data_width=32, address_width=32, addressing="word")
                 up_converter   = wishbone.UpConverter(self.wb32, wb64)
                 down_converter = wishbone.DownConverter(wb64, wb32)
                 self.submodules += up_converter, down_converter
@@ -70,7 +70,7 @@ class TestWishbone(unittest.TestCase):
 
         class DUT(Module):
             def __init__(self):
-                self.wb = wishbone.Interface(bursting=True)
+                self.wb = wishbone.Interface(data_width=32, address_width=32, addressing="word", bursting=True)
                 wishbone_mem = wishbone.SRAM(32, bus=self.wb)
                 self.submodules += wishbone_mem
 
@@ -91,7 +91,7 @@ class TestWishbone(unittest.TestCase):
 
         class DUT(Module):
             def __init__(self):
-                self.wb = wishbone.Interface(bursting=True)
+                self.wb = wishbone.Interface(data_width=32, address_width=32, addressing="word", bursting=True)
                 wishbone_mem = wishbone.SRAM(32, bus=self.wb)
                 self.submodules += wishbone_mem
 
@@ -111,7 +111,7 @@ class TestWishbone(unittest.TestCase):
 
         class DUT(Module):
             def __init__(self):
-                self.wb = wishbone.Interface(bursting=True)
+                self.wb = wishbone.Interface(data_width=32, address_width=32, addressing="word", bursting=True)
                 wishbone_mem = wishbone.SRAM(32, bus=self.wb)
                 self.submodules += wishbone_mem