From 0042a0280744c31988d04b16d1b84b9848955047 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 24 Feb 2020 13:24:32 +0100 Subject: [PATCH] interconnect/axi: remove bus_name on connect_to_pads --- litex/soc/interconnect/axi.py | 2 +- litex/tools/litex_gen.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/litex/soc/interconnect/axi.py b/litex/soc/interconnect/axi.py index 58755b92b..905ef5867 100644 --- a/litex/soc/interconnect/axi.py +++ b/litex/soc/interconnect/axi.py @@ -110,7 +110,7 @@ class AXILiteInterface(Record): ios = [(bus_name , 0) + tuple(subsignals)] return ios - def connect_to_pads(self, pads, bus_name, mode="master"): + def connect_to_pads(self, pads, mode="master"): assert mode in ["slave", "master"] r = [] def swap_mode(mode): return "master" if mode == "slave" else "slave" diff --git a/litex/tools/litex_gen.py b/litex/tools/litex_gen.py index 28fc95317..465be327f 100755 --- a/litex/tools/litex_gen.py +++ b/litex/tools/litex_gen.py @@ -102,7 +102,7 @@ class LiteXCore(SoCMini): self.bus.add_master(master=wb_bus) platform.add_extension(axi_bus.get_ios("axi")) axi_pads = platform.request("axi") - self.comb += axi_bus.connect_to_pads(axi_pads, "axi", mode="slave") + self.comb += axi_bus.connect_to_pads(axi_pads, mode="slave") # IRQs for name, loc in sorted(self.irq.locs.items()):