From 004924a3190f5d6b58a213f499e7f8460f9f42c6 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 8 Oct 2020 11:34:57 +0200
Subject: [PATCH] soc/interconnect/csr: expose re on CSRStatus (to allow
 triggering actions on CSRStatus writes).

---
 litex/soc/interconnect/csr.py | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/litex/soc/interconnect/csr.py b/litex/soc/interconnect/csr.py
index 41fca9b24..7320311a5 100644
--- a/litex/soc/interconnect/csr.py
+++ b/litex/soc/interconnect/csr.py
@@ -295,6 +295,7 @@ class CSRStatus(_CompoundCSR):
         self.description = description
         self.status      = Signal(self.size, reset=reset)
         self.we          = Signal()
+        self.re          = Signal()
         for field in fields:
             self.comb += self.status[field.offset:field.offset + field.size].eq(getattr(self.fields, field.name))
 
@@ -306,6 +307,7 @@ class CSRStatus(_CompoundCSR):
             self.comb += sc.w.eq(self.status[i*busword:i*busword+nbits])
             self.simple_csrs.append(sc)
         self.comb += self.we.eq(sc.we)
+        self.comb += self.re.eq(sc.re)
 
     def read(self):
         """Read method for simulation."""