From 004c96b508644c17a627337459e87ac0a7bcc8a9 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 9 Sep 2019 15:12:08 +0200 Subject: [PATCH] soc/itnegration: update litedram --- litex/soc/integration/builder.py | 4 ++-- litex/soc/integration/soc_sdram.py | 7 ++++--- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/litex/soc/integration/builder.py b/litex/soc/integration/builder.py index 28fc145aa..b656f9983 100644 --- a/litex/soc/integration/builder.py +++ b/litex/soc/integration/builder.py @@ -16,7 +16,7 @@ import shutil from litex.build.tools import write_to_file from litex.soc.integration import cpu_interface, soc_core, soc_sdram -from litedram import sdram_init +from litedram.init import get_sdram_phy_c_header __all__ = ["soc_software_packages", "soc_directory", "Builder", "builder_args", "builder_argdict"] @@ -125,7 +125,7 @@ class Builder: if hasattr(self.soc, "sdram"): write_to_file( os.path.join(generated_dir, "sdram_phy.h"), - sdram_init.get_sdram_phy_c_header( + get_sdram_phy_c_header( self.soc.sdram.controller.settings.phy, self.soc.sdram.controller.settings.timing)) diff --git a/litex/soc/integration/soc_sdram.py b/litex/soc/integration/soc_sdram.py index 1706ae41f..c148fac87 100644 --- a/litex/soc/integration/soc_sdram.py +++ b/litex/soc/integration/soc_sdram.py @@ -20,7 +20,7 @@ __all__ = ["SoCSDRAM", "soc_sdram_args", "soc_sdram_argdict"] class ControllerInjector(Module, AutoCSR): - def __init__(self, phy, geom_settings, timing_settings, **kwargs): + def __init__(self, phy, geom_settings, timing_settings, clk_freq, **kwargs): self.submodules.dfii = dfii.DFIInjector( geom_settings.addressbits, geom_settings.bankbits, @@ -30,7 +30,8 @@ class ControllerInjector(Module, AutoCSR): self.comb += self.dfii.master.connect(phy.dfi) self.submodules.controller = controller = core.LiteDRAMController( - phy.settings, geom_settings, timing_settings, **kwargs) + phy.settings, geom_settings, timing_settings, + clk_freq, **kwargs) self.comb += controller.dfi.connect(self.dfii.slave) self.submodules.crossbar = core.LiteDRAMCrossbar(controller.interface) @@ -64,7 +65,7 @@ class SoCSDRAM(SoCCore): self._sdram_phy.append(phy) # encapsulate in list to prevent CSR scanning self.submodules.sdram = ControllerInjector( - phy, geom_settings, timing_settings, **kwargs) + phy, geom_settings, timing_settings, self.clk_freq, **kwargs) main_ram_size = 2**(geom_settings.bankbits + geom_settings.rowbits +