From 00f29a3497a443a1acf4e2b5e12f60bbf71f35b1 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 12 Oct 2022 11:57:21 +0200
Subject: [PATCH] build: Rename VHDLWrapper to VHD2VConverter (more explicit).

---
 litex/build/{VHDLWrapper.py => vhd2v_converter.py} | 6 +++---
 litex/soc/cores/cpu/neorv32/core.py                | 6 +++---
 2 files changed, 6 insertions(+), 6 deletions(-)
 rename litex/build/{VHDLWrapper.py => vhd2v_converter.py} (96%)

diff --git a/litex/build/VHDLWrapper.py b/litex/build/vhd2v_converter.py
similarity index 96%
rename from litex/build/VHDLWrapper.py
rename to litex/build/vhd2v_converter.py
index 8bdb61a8b..6ff629c89 100644
--- a/litex/build/VHDLWrapper.py
+++ b/litex/build/vhd2v_converter.py
@@ -9,11 +9,11 @@ import os
 
 from migen import *
 
-# VHDLWrapper --------------------------------------------------------------------------------------
+# VHD2V Converter ----------------------------------------------------------------------------------
 
-class VHDLWrapper(Module):
+class VHD2VConverter(Module):
     """
-    VHDLWrapper simplify use of VHDL code: used to convert with ghdl the code if
+    VHD2VConverter simplify use of VHDL code: used to convert with ghdl the code if
     needed or simply pass list of files to platform. May also add an Instance.
     Attributes
     ==========
diff --git a/litex/soc/cores/cpu/neorv32/core.py b/litex/soc/cores/cpu/neorv32/core.py
index bffa497b9..32c93e545 100644
--- a/litex/soc/cores/cpu/neorv32/core.py
+++ b/litex/soc/cores/cpu/neorv32/core.py
@@ -8,7 +8,7 @@ import os
 
 from migen import *
 
-from litex.build.VHDLWrapper import *
+from litex.build.vhd2v_converter import *
 
 from litex.soc.interconnect import wishbone
 from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32
@@ -99,7 +99,7 @@ class NEORV32(CPU):
             i_wb_err_i    = idbus.err,
         )
 
-        self.submodules.vhdlwrapper = VHDLWrapper(platform,
+        self.submodules.vhd2v_converter = VHD2VConverter(platform,
             top_entity    = "neorv32_litex_core_complex",
             build_dir     = os.path.abspath(os.path.dirname(__file__)),
             work_package  = "neorv32",
@@ -160,7 +160,7 @@ class NEORV32(CPU):
         # Download VHDL sources (if not already present).
         for directory, vhds in sources.items():
             for vhd in vhds:
-                self.vhdlwrapper.add_source(os.path.join(cdir, vhd))
+                self.vhd2v_converter.add_source(os.path.join(cdir, vhd))
                 if not os.path.exists(os.path.join(cdir, vhd)):
                     os.system(f"wget https://raw.githubusercontent.com/stnolting/neorv32/main/rtl/{directory}/{vhd} -P {cdir}")