From 014db664440525abcf6442ce2493ddcf257025dd Mon Sep 17 00:00:00 2001
From: Gabriel Somlo <gsomlo@gmail.com>
Date: Thu, 31 Oct 2019 16:23:36 -0400
Subject: [PATCH] soc_sdram: remove upper limit on usable main RAM

Revert commit #68a503174.
---
 litex/soc/integration/soc_sdram.py | 1 -
 1 file changed, 1 deletion(-)

diff --git a/litex/soc/integration/soc_sdram.py b/litex/soc/integration/soc_sdram.py
index f16e596ad..71f54b177 100644
--- a/litex/soc/integration/soc_sdram.py
+++ b/litex/soc/integration/soc_sdram.py
@@ -61,7 +61,6 @@ class SoCSDRAM(SoCCore):
         main_ram_size = 2**(geom_settings.bankbits +
                             geom_settings.rowbits +
                             geom_settings.colbits)*phy.settings.databits//8
-        main_ram_size = min(main_ram_size, 0x20000000) # FIXME: limit to 512MB for now
 
         # SoC [<--> L2 Cache] <--> LiteDRAM ----------------------------------------------------
         if self.cpu.name == "rocket":