From 015b65fe88b5b59899869e7ca30126986c478ed3 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 25 Sep 2019 14:09:44 +0200 Subject: [PATCH] targets/ulx3s: revert to cl=2 --- litex/boards/targets/ulx3s.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/boards/targets/ulx3s.py b/litex/boards/targets/ulx3s.py index 4a80ee6fb..f1e21ba73 100755 --- a/litex/boards/targets/ulx3s.py +++ b/litex/boards/targets/ulx3s.py @@ -63,7 +63,7 @@ class BaseSoC(SoCSDRAM): self.submodules.crg = _CRG(platform, sys_clk_freq) if not self.integrated_main_ram_size: - self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cl=3) + self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cl=2) sdram_module = MT48LC16M16(sys_clk_freq, "1:1") self.register_sdram(self.sdrphy, sdram_module.geom_settings,