diff --git a/milkymist/dvisampler/edid.py b/milkymist/dvisampler/edid.py
index 48fb69e28..89c29799b 100644
--- a/milkymist/dvisampler/edid.py
+++ b/milkymist/dvisampler/edid.py
@@ -33,9 +33,9 @@ class EDID(Module, AutoReg):
 		_sda_i_async = Signal()
 		self.sync += _sda_drv_reg.eq(sda_drv)
 		self.specials += [
-			MultiReg(self.scl, "ext", scl_i, "sys"),
+			MultiReg(self.scl, scl_i, "sys"),
 			Tristate(self.sda, 0, _sda_drv_reg, _sda_i_async),
-			MultiReg(_sda_i_async, "ext", sda_i, "sys")
+			MultiReg(_sda_i_async, sda_i, "sys")
 		]
 
 		# FIXME: understand what is really going on here and get rid of that workaround
diff --git a/milkymist/uart/__init__.py b/milkymist/uart/__init__.py
index 8dd903f09..8a129746c 100644
--- a/milkymist/uart/__init__.py
+++ b/milkymist/uart/__init__.py
@@ -59,7 +59,7 @@ class UART(Module, AutoReg):
 		
 		# RX
 		rx = Signal()
-		self.specials += MultiReg(self.rx, "ext", rx, "sys")
+		self.specials += MultiReg(self.rx, rx, "sys")
 		rx_r = Signal()
 		rx_reg = Signal(8)
 		rx_bitcount = Signal(4)