diff --git a/litex/soc/cores/cpu/naxriscv/core.py b/litex/soc/cores/cpu/naxriscv/core.py
index 90d471790..cddc2f934 100755
--- a/litex/soc/cores/cpu/naxriscv/core.py
+++ b/litex/soc/cores/cpu/naxriscv/core.py
@@ -298,7 +298,7 @@ class NaxRiscv(CPU):
         soc.irq.add("timer0", n=1)
 
         # Add OpenSBI region.
-        soc.add_memory_region("opensbi", self.mem_map["main_ram"] + 0x00f0_0000, 0x8_0000, type="cached+linker")
+        soc.bus.add_region("opensbi", soc_region_cls(origin=self.mem_map["main_ram"] + 0x00f0_0000, size=0x8_0000, cached=True, linker=True))
 
         # Define ISA.
         soc.add_config("CPU_ISA", NaxRiscv.get_arch())
diff --git a/litex/soc/cores/cpu/rocket/core.py b/litex/soc/cores/cpu/rocket/core.py
index 5af519d11..fabd365a5 100644
--- a/litex/soc/cores/cpu/rocket/core.py
+++ b/litex/soc/cores/cpu/rocket/core.py
@@ -360,10 +360,10 @@ class Rocket(CPU):
         # Get CPU Params.
         mem_dw, mmio_dw, num_cores = CPU_PARAMS[self.variant]
 
-        # Add OpenSBI/PLIC/CLINT regions. # FIXME: Just here for .dts generation through json2ds.
-        soc.add_memory_region("opensbi", self.mem_map["main_ram"] + 0x00f0_0000,   0x8_0000, type="linker")
-        soc.add_memory_region("plic",    soc.mem_map.get("plic")               , 0x400_0000, type="cached+linker")
-        soc.add_memory_region("clint",   soc.mem_map.get("clint")              ,   0x1_0000, type="cached+linker")
+        # Add OpenSBI/PLIC/CLINT regions.
+        soc.bus.add_region("opensbi", soc_region_cls(origin=self.mem_map["main_ram"] + 0x00f0_0000, size= 0x8_0000, cached=False, linker=True)) # CHECKME.
+        soc.bus.add_region("plic",    soc_region_cls(origin=soc.mem_map.get("plic"),                size=0x40_0000, cached=True,  linker=True))
+        soc.bus.add_region("clint",   soc_region_cls(origin=soc.mem_map.get("clint"),               size= 0x1_0000, cached=True,  linker=True))
 
         # Define number of CPUs
         soc.add_config("CPU_COUNT", num_cores)
diff --git a/litex/soc/cores/cpu/vexriscv_smp/core.py b/litex/soc/cores/cpu/vexriscv_smp/core.py
index a938b1fd6..e8a1ce4ee 100755
--- a/litex/soc/cores/cpu/vexriscv_smp/core.py
+++ b/litex/soc/cores/cpu/vexriscv_smp/core.py
@@ -397,7 +397,7 @@ class VexRiscvSMP(CPU):
         soc.irq.add("timer0", n=1)
 
         # Add OpenSBI region.
-        soc.add_memory_region("opensbi", self.mem_map["main_ram"] + 0x00f0_0000, 0x8_0000, type="cached+linker")
+        soc.bus.add_region("opensbi", soc_region_cls(origin=self.mem_map["main_ram"] + 0x00f0_0000, size=0x8_0000, cached=True, linker=True))
 
         # Define number of CPUs
         soc.add_config("CPU_COUNT", VexRiscvSMP.cpu_count)