diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index cb6f5733e..63b44a4fd 100755
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -847,7 +847,7 @@ class SoC(LiteXModule, SoCCoreCompat):
 
         # SoC attributes ---------------------------------------------------------------------------
         self.platform     = platform
-        self.sys_clk_freq = sys_clk_freq
+        self.sys_clk_freq = int(sys_clk_freq) # Do conversion to int here to allow passing float to SoC.
         self.constants    = {}
         self.csr_regions  = {}
 
diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index dc6ae7272..1ad8fd4c4 100644
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -111,7 +111,7 @@ class SoCCore(LiteXSoC):
         # Others
         **kwargs):
 
-        # New LiteXSoC class ----------------------------------------------------------------------------
+        # New LiteXSoC class -----------------------------------------------------------------------
         LiteXSoC.__init__(self, platform, clk_freq,
             bus_standard         = bus_standard,
             bus_data_width       = bus_data_width,