From 01d980b0622dbf9d10a06331a68f94889c667551 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 10 Feb 2015 15:22:06 +0100 Subject: [PATCH] move more things to common files --- liteeth/core/ip/__init__.py | 71 ---------------------------------- liteeth/core/ip/common.py | 71 ++++++++++++++++++++++++++++++++++ liteeth/core/udp/__init__.py | 46 ---------------------- liteeth/core/udp/common.py | 46 ++++++++++++++++++++++ liteeth/mac/__init__.py | 32 +-------------- liteeth/mac/common.py | 57 +++++++++++++++++++++++++++ liteeth/mac/frontend/common.py | 27 ------------- 7 files changed, 175 insertions(+), 175 deletions(-) create mode 100644 liteeth/mac/common.py delete mode 100644 liteeth/mac/frontend/common.py diff --git a/liteeth/core/ip/__init__.py b/liteeth/core/ip/__init__.py index 8e522a994..00204aa49 100644 --- a/liteeth/core/ip/__init__.py +++ b/liteeth/core/ip/__init__.py @@ -1,77 +1,6 @@ from liteeth.common import * -from liteeth.generic.depacketizer import LiteEthDepacketizer -from liteeth.generic.packetizer import LiteEthPacketizer -from liteeth.generic.crossbar import LiteEthCrossbar from liteeth.core.ip.common import * -class LiteEthIPV4Depacketizer(LiteEthDepacketizer): - def __init__(self): - LiteEthDepacketizer.__init__(self, - eth_mac_description(8), - eth_ipv4_description(8), - ipv4_header, - ipv4_header_len) - -class LiteEthIPV4Packetizer(LiteEthPacketizer): - def __init__(self): - LiteEthPacketizer.__init__(self, - eth_ipv4_description(8), - eth_mac_description(8), - ipv4_header, - ipv4_header_len) - -class LiteEthIPV4Crossbar(LiteEthCrossbar): - def __init__(self): - LiteEthCrossbar.__init__(self, LiteEthIPV4MasterPort, "protocol") - - def get_port(self, protocol): - if protocol in self.users.keys(): - raise ValueError("Protocol {0:#x} already assigned".format(protocol)) - port = LiteEthIPV4UserPort(8) - self.users[protocol] = port - return port - -class LiteEthIPV4Checksum(Module): - def __init__(self, words_per_clock_cycle=1, skip_checksum=False): - self.reset = Signal() # XXX FIXME InsertReset generates incorrect verilog - self.ce = Signal() # XXX FIXME InsertCE generates incorrect verilog - self.header = Signal(ipv4_header_len*8) - self.value = Signal(16) - self.done = Signal() - ### - s = Signal(17) - r = Signal(17) - n_cycles = 0 - for i in range(ipv4_header_len//2): - if skip_checksum and (i == ipv4_header["checksum"].byte//2): - pass - else: - s_next = Signal(17) - r_next = Signal(17) - self.comb += s_next.eq(r + self.header[i*16:(i+1)*16]) - r_next_eq = r_next.eq(Cat(s_next[:16]+s_next[16], Signal())) - if (i%words_per_clock_cycle) != 0: - self.comb += r_next_eq - else: - self.sync += \ - If(self.reset, - r_next.eq(0) - ).Elif(self.ce & ~self.done, - r_next_eq - ) - n_cycles += 1 - s, r = s_next, r_next - self.comb += self.value.eq(~Cat(r[8:16], r[:8])) - - if not skip_checksum: - n_cycles += 1 - self.submodules.counter = counter = Counter(max=n_cycles+1) - self.comb += [ - counter.reset.eq(self.reset), - counter.ce.eq(self.ce & ~self.done), - self.done.eq(counter.value == n_cycles) - ] - class LiteEthIPTX(Module): def __init__(self, mac_address, ip_address, arp_table): self.sink = sink = Sink(eth_ipv4_user_description(8)) diff --git a/liteeth/core/ip/common.py b/liteeth/core/ip/common.py index b61c27c95..338033ea6 100644 --- a/liteeth/core/ip/common.py +++ b/liteeth/core/ip/common.py @@ -1,4 +1,23 @@ from liteeth.common import * +from liteeth.generic.depacketizer import LiteEthDepacketizer +from liteeth.generic.packetizer import LiteEthPacketizer +from liteeth.generic.crossbar import LiteEthCrossbar + +class LiteEthIPV4Depacketizer(LiteEthDepacketizer): + def __init__(self): + LiteEthDepacketizer.__init__(self, + eth_mac_description(8), + eth_ipv4_description(8), + ipv4_header, + ipv4_header_len) + +class LiteEthIPV4Packetizer(LiteEthPacketizer): + def __init__(self): + LiteEthPacketizer.__init__(self, + eth_ipv4_description(8), + eth_mac_description(8), + ipv4_header, + ipv4_header_len) class LiteEthIPV4MasterPort: def __init__(self, dw): @@ -27,3 +46,55 @@ class LiteEthIPV4SlavePort: class LiteEthIPV4UserPort(LiteEthIPV4SlavePort): def __init__(self, dw): LiteEthIPV4SlavePort.__init__(self, dw) + +class LiteEthIPV4Crossbar(LiteEthCrossbar): + def __init__(self): + LiteEthCrossbar.__init__(self, LiteEthIPV4MasterPort, "protocol") + + def get_port(self, protocol): + if protocol in self.users.keys(): + raise ValueError("Protocol {0:#x} already assigned".format(protocol)) + port = LiteEthIPV4UserPort(8) + self.users[protocol] = port + return port + +class LiteEthIPV4Checksum(Module): + def __init__(self, words_per_clock_cycle=1, skip_checksum=False): + self.reset = Signal() # XXX FIXME InsertReset generates incorrect verilog + self.ce = Signal() # XXX FIXME InsertCE generates incorrect verilog + self.header = Signal(ipv4_header_len*8) + self.value = Signal(16) + self.done = Signal() + ### + s = Signal(17) + r = Signal(17) + n_cycles = 0 + for i in range(ipv4_header_len//2): + if skip_checksum and (i == ipv4_header["checksum"].byte//2): + pass + else: + s_next = Signal(17) + r_next = Signal(17) + self.comb += s_next.eq(r + self.header[i*16:(i+1)*16]) + r_next_eq = r_next.eq(Cat(s_next[:16]+s_next[16], Signal())) + if (i%words_per_clock_cycle) != 0: + self.comb += r_next_eq + else: + self.sync += \ + If(self.reset, + r_next.eq(0) + ).Elif(self.ce & ~self.done, + r_next_eq + ) + n_cycles += 1 + s, r = s_next, r_next + self.comb += self.value.eq(~Cat(r[8:16], r[:8])) + + if not skip_checksum: + n_cycles += 1 + self.submodules.counter = counter = Counter(max=n_cycles+1) + self.comb += [ + counter.reset.eq(self.reset), + counter.ce.eq(self.ce & ~self.done), + self.done.eq(counter.value == n_cycles) + ] diff --git a/liteeth/core/udp/__init__.py b/liteeth/core/udp/__init__.py index 55f624149..16ad1b8be 100644 --- a/liteeth/core/udp/__init__.py +++ b/liteeth/core/udp/__init__.py @@ -1,52 +1,6 @@ from liteeth.common import * -from liteeth.generic.depacketizer import LiteEthDepacketizer -from liteeth.generic.packetizer import LiteEthPacketizer -from liteeth.generic.crossbar import LiteEthCrossbar from liteeth.core.udp.common import * -class LiteEthUDPDepacketizer(LiteEthDepacketizer): - def __init__(self): - LiteEthDepacketizer.__init__(self, - eth_ipv4_user_description(8), - eth_udp_description(8), - udp_header, - udp_header_len) - -class LiteEthUDPPacketizer(LiteEthPacketizer): - def __init__(self): - LiteEthPacketizer.__init__(self, - eth_udp_description(8), - eth_ipv4_user_description(8), - udp_header, - udp_header_len) - -class LiteEthUDPCrossbar(LiteEthCrossbar): - def __init__(self): - LiteEthCrossbar.__init__(self, LiteEthUDPMasterPort, "dst_port") - - def get_port(self, udp_port, dw=8): - if udp_port in self.users.keys(): - raise ValueError("Port {0:#x} already assigned".format(udp_port)) - user_port = LiteEthUDPUserPort(dw) - internal_port = LiteEthUDPUserPort(8) - if dw != 8: - converter = Converter(eth_udp_user_description(user_port.dw), eth_udp_user_description(8)) - self.submodules += converter - self.comb += [ - Record.connect(user_port.sink, converter.sink), - Record.connect(converter.source, internal_port.sink) - ] - converter = Converter(eth_udp_user_description(8), eth_udp_user_description(user_port.dw)) - self.submodules += converter - self.comb += [ - Record.connect(internal_port.source, converter.sink), - Record.connect(converter.source, user_port.source) - ] - self.users[udp_port] = internal_port - else: - self.users[udp_port] = user_port - return user_port - class LiteEthUDPTX(Module): def __init__(self, ip_address): self.sink = sink = Sink(eth_udp_user_description(8)) diff --git a/liteeth/core/udp/common.py b/liteeth/core/udp/common.py index eed6f1d24..98fe9be36 100644 --- a/liteeth/core/udp/common.py +++ b/liteeth/core/udp/common.py @@ -1,4 +1,23 @@ from liteeth.common import * +from liteeth.generic.depacketizer import LiteEthDepacketizer +from liteeth.generic.packetizer import LiteEthPacketizer +from liteeth.generic.crossbar import LiteEthCrossbar + +class LiteEthUDPDepacketizer(LiteEthDepacketizer): + def __init__(self): + LiteEthDepacketizer.__init__(self, + eth_ipv4_user_description(8), + eth_udp_description(8), + udp_header, + udp_header_len) + +class LiteEthUDPPacketizer(LiteEthPacketizer): + def __init__(self): + LiteEthPacketizer.__init__(self, + eth_udp_description(8), + eth_ipv4_user_description(8), + udp_header, + udp_header_len) class LiteEthUDPMasterPort: def __init__(self, dw): @@ -27,3 +46,30 @@ class LiteEthUDPSlavePort: class LiteEthUDPUserPort(LiteEthUDPSlavePort): def __init__(self, dw): LiteEthUDPSlavePort.__init__(self, dw) + +class LiteEthUDPCrossbar(LiteEthCrossbar): + def __init__(self): + LiteEthCrossbar.__init__(self, LiteEthUDPMasterPort, "dst_port") + + def get_port(self, udp_port, dw=8): + if udp_port in self.users.keys(): + raise ValueError("Port {0:#x} already assigned".format(udp_port)) + user_port = LiteEthUDPUserPort(dw) + internal_port = LiteEthUDPUserPort(8) + if dw != 8: + converter = Converter(eth_udp_user_description(user_port.dw), eth_udp_user_description(8)) + self.submodules += converter + self.comb += [ + Record.connect(user_port.sink, converter.sink), + Record.connect(converter.source, internal_port.sink) + ] + converter = Converter(eth_udp_user_description(8), eth_udp_user_description(user_port.dw)) + self.submodules += converter + self.comb += [ + Record.connect(internal_port.source, converter.sink), + Record.connect(converter.source, user_port.source) + ] + self.users[udp_port] = internal_port + else: + self.users[udp_port] = user_port + return user_port diff --git a/liteeth/mac/__init__.py b/liteeth/mac/__init__.py index e2032d89a..e7bf6d66c 100644 --- a/liteeth/mac/__init__.py +++ b/liteeth/mac/__init__.py @@ -1,38 +1,8 @@ from liteeth.common import * -from liteeth.generic.depacketizer import LiteEthDepacketizer -from liteeth.generic.packetizer import LiteEthPacketizer -from liteeth.generic.crossbar import LiteEthCrossbar +from liteeth.mac.common import * from liteeth.mac.core import LiteEthMACCore -from liteeth.mac.frontend.common import * from liteeth.mac.frontend.wishbone import LiteEthMACWishboneInterface -class LiteEthMACDepacketizer(LiteEthDepacketizer): - def __init__(self): - LiteEthDepacketizer.__init__(self, - eth_phy_description(8), - eth_mac_description(8), - mac_header, - mac_header_len) - -class LiteEthMACPacketizer(LiteEthPacketizer): - def __init__(self): - LiteEthPacketizer.__init__(self, - eth_mac_description(8), - eth_phy_description(8), - mac_header, - mac_header_len) - -class LiteEthMACCrossbar(LiteEthCrossbar): - def __init__(self): - LiteEthCrossbar.__init__(self, LiteEthMACMasterPort, "ethernet_type") - - def get_port(self, ethernet_type): - port = LiteEthMACUserPort(8) - if ethernet_type in self.users.keys(): - raise ValueError("Ethernet type {0:#x} already assigned".format(ethernet_type)) - self.users[ethernet_type] = port - return port - class LiteEthMAC(Module, AutoCSR): def __init__(self, phy, dw, interface="crossbar", endianness="big", with_hw_preamble_crc=True): diff --git a/liteeth/mac/common.py b/liteeth/mac/common.py new file mode 100644 index 000000000..f82faecb9 --- /dev/null +++ b/liteeth/mac/common.py @@ -0,0 +1,57 @@ +from liteeth.common import * +from liteeth.generic.depacketizer import LiteEthDepacketizer +from liteeth.generic.packetizer import LiteEthPacketizer +from liteeth.generic.crossbar import LiteEthCrossbar + +class LiteEthMACDepacketizer(LiteEthDepacketizer): + def __init__(self): + LiteEthDepacketizer.__init__(self, + eth_phy_description(8), + eth_mac_description(8), + mac_header, + mac_header_len) + +class LiteEthMACPacketizer(LiteEthPacketizer): + def __init__(self): + LiteEthPacketizer.__init__(self, + eth_mac_description(8), + eth_phy_description(8), + mac_header, + mac_header_len) + +class LiteEthMACMasterPort: + def __init__(self, dw): + self.source = Source(eth_mac_description(dw)) + self.sink = Sink(eth_mac_description(dw)) + + def connect(self, slave): + return [ + Record.connect(self.source, slave.sink), + Record.connect(slave.source, self.sink) + ] + +class LiteEthMACSlavePort: + def __init__(self, dw): + self.sink = Sink(eth_mac_description(dw)) + self.source = Source(eth_mac_description(dw)) + + def connect(self, master): + return [ + Record.connect(self.sink, master.source), + Record.connect(master.sink, self.source) + ] + +class LiteEthMACUserPort(LiteEthMACSlavePort): + def __init__(self, dw): + LiteEthMACSlavePort.__init__(self, dw) + +class LiteEthMACCrossbar(LiteEthCrossbar): + def __init__(self): + LiteEthCrossbar.__init__(self, LiteEthMACMasterPort, "ethernet_type") + + def get_port(self, ethernet_type): + port = LiteEthMACUserPort(8) + if ethernet_type in self.users.keys(): + raise ValueError("Ethernet type {0:#x} already assigned".format(ethernet_type)) + self.users[ethernet_type] = port + return port diff --git a/liteeth/mac/frontend/common.py b/liteeth/mac/frontend/common.py deleted file mode 100644 index b945ded45..000000000 --- a/liteeth/mac/frontend/common.py +++ /dev/null @@ -1,27 +0,0 @@ -from liteeth.common import * - -class LiteEthMACMasterPort: - def __init__(self, dw): - self.source = Source(eth_mac_description(dw)) - self.sink = Sink(eth_mac_description(dw)) - - def connect(self, slave): - return [ - Record.connect(self.source, slave.sink), - Record.connect(slave.source, self.sink) - ] - -class LiteEthMACSlavePort: - def __init__(self, dw): - self.sink = Sink(eth_mac_description(dw)) - self.source = Source(eth_mac_description(dw)) - - def connect(self, master): - return [ - Record.connect(self.sink, master.source), - Record.connect(master.sink, self.source) - ] - -class LiteEthMACUserPort(LiteEthMACSlavePort): - def __init__(self, dw): - LiteEthMACSlavePort.__init__(self, dw)