From 022ac26c22891e71b50271590f7a9f96f8168e9c Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 17 Mar 2015 12:42:36 +0100 Subject: [PATCH] mibuild/lattice: add LatticeAsyncResetSynchronizer --- mibuild/lattice/common.py | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/mibuild/lattice/common.py b/mibuild/lattice/common.py index e238a327a..1f5654c48 100644 --- a/mibuild/lattice/common.py +++ b/mibuild/lattice/common.py @@ -1,6 +1,21 @@ from migen.fhdl.std import * from migen.genlib.io import * +class LatticeAsyncResetSynchronizerImpl(Module): + def __init__(self, cd, async_reset): + rst1 = Signal() + self.specials += [ + Instance("FD1S3BX", i_D=0, i_PD=async_reset, + i_CK=cd.clk, o_Q=rst1), + Instance("FD1S3BX", i_D=rst1, i_PD=async_reset, + i_CK=cd.clk, o_Q=cd.rst) + ] + +class LatticeAsyncResetSynchronizer: + @staticmethod + def lower(dr): + return LatticeAsyncResetSynchronizerImpl(dr.cd, dr.async_reset) + class LatticeDDROutputImpl(Module): def __init__(self, i1, i2, o, clk): self.specials += Instance("ODDRA", @@ -14,5 +29,6 @@ class LatticeDDROutput: return LatticeDDROutputImpl(dr.i1, dr.i2, dr.o, dr.clk) lattice_special_overrides = { + AsyncResetSynchronizer: LatticeAsyncResetSynchronizer, DDROutput: LatticeDDROutput }