diff --git a/litex/soc/cores/clock/lattice_ecp5.py b/litex/soc/cores/clock/lattice_ecp5.py
index fd6cdbd4f..4b0f5c75e 100644
--- a/litex/soc/cores/clock/lattice_ecp5.py
+++ b/litex/soc/cores/clock/lattice_ecp5.py
@@ -97,6 +97,9 @@ class ECP5PLL(Module):
                                     break
                             if not valid:
                                 all_valid = False
+                        if self.nclkouts == self.nclkouts_max and not config["clkfb"]:
+                            # If there is no output suitable for feedback and no spare, not valid
+                            all_valid = False
                     else:
                         all_valid = False
                     if all_valid:
@@ -159,4 +162,6 @@ class ECP5PLL(Module):
             self.params[f"p_CLKO{n_to_l[n]}_FPHASE"] = 0
             self.params[f"p_CLKO{n_to_l[n]}_CPHASE"] = cphase
             self.params[f"o_CLKO{n_to_l[n]}"]        = clk
+            if f > 0:  # i.e. not a feedback-only clock
+                self.params["attr"].append((f"FREQUENCY_PIN_CLKO{n_to_l[n]}", str(f/1e6)))
         self.specials += Instance("EHXPLLL", **self.params)
diff --git a/test/test_clock.py b/test/test_clock.py
index a1795149c..8d5fce8ac 100644
--- a/test/test_clock.py
+++ b/test/test_clock.py
@@ -121,6 +121,15 @@ class TestClock(unittest.TestCase):
         pll.expose_dpa()
         pll.compute_config()
 
+        # Test corner cases that have historically had trouble:
+        pll = ECP5PLL()
+        pll.register_clkin(Signal(), 100e6)
+        pll.create_clkout(ClockDomain("clkout1"), 350e6)
+        pll.create_clkout(ClockDomain("clkout2"), 350e6)
+        pll.create_clkout(ClockDomain("clkout3"), 175e6)
+        pll.create_clkout(ClockDomain("clkout4"), 175e6)
+        pll.compute_config()
+
     # Lattice / NX
     def test_nxpll(self):
         pll = NXPLL()