diff --git a/litex/soc/cores/ram/lattice_ice40.py b/litex/soc/cores/ram/lattice_ice40.py
index ad0acee74..08ea05967 100644
--- a/litex/soc/cores/ram/lattice_ice40.py
+++ b/litex/soc/cores/ram/lattice_ice40.py
@@ -7,6 +7,9 @@
 # SPDX-License-Identifier: BSD-2-Clause
 
 from migen import *
+
+from litex.gen import *
+
 from litex.soc.interconnect import wishbone
 
 kB = 1024
@@ -22,7 +25,7 @@ of 4 SPRAMs for this, so the only other valid config is using all 4 SPRAMs by de
 
 """
 
-class Up5kSPRAM(Module):
+class Up5kSPRAM(LiteXModule):
     def __init__(self, width=32, size=64*kB):
         self.bus = wishbone.Interface(width)
 
diff --git a/litex/soc/cores/ram/lattice_nx.py b/litex/soc/cores/ram/lattice_nx.py
index 7dce4089f..836c1a314 100644
--- a/litex/soc/cores/ram/lattice_nx.py
+++ b/litex/soc/cores/ram/lattice_nx.py
@@ -8,6 +8,9 @@
 # SPDX-License-Identifier: BSD-2-Clause
 
 from migen import *
+
+from litex.gen import *
+
 from litex.soc.interconnect import wishbone
 
 kB = 1024
@@ -48,7 +51,7 @@ def initval_parameters(contents, width):
     return parameters
 
 
-class NXLRAM(Module):
+class NXLRAM(LiteXModule):
     def __init__(self, width=32, size=128*kB, init=[]):
         self.bus = wishbone.Interface(width)
         assert width in [32, 64]
diff --git a/litex/soc/cores/ram/xilinx_fifo_sync_macro.py b/litex/soc/cores/ram/xilinx_fifo_sync_macro.py
index a1a5ae04f..89ea80f84 100644
--- a/litex/soc/cores/ram/xilinx_fifo_sync_macro.py
+++ b/litex/soc/cores/ram/xilinx_fifo_sync_macro.py
@@ -1,8 +1,16 @@
+#
+# This file is part of LiteX.
+#
+# Copyright (c) 2022 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: BSD-2-Clause
+
 from migen import *
 
+from litex.gen import *
+
 from litex.soc.interconnect.stream import SyncFIFO
 
-class FIFOSyncMacro(Module, Record):
+class FIFOSyncMacro(LiteXModule, Record):
     """FIFOSyncMacro
 
     Provides an equivalent of Xilinx' FIFO_SYNC_MACRO which is a unimacro dedicated for 7 series
@@ -86,7 +94,7 @@ class FIFOSyncMacro(Module, Record):
 
             self.fifo_depth = fifo_depth = (int)(fifo_size * 1024 / macro_data_width)
 
-            self.submodules.fifo = fifo = ResetInserter()(SyncFIFO([("data", data_width)], fifo_depth))
+            self.fifo = fifo = ResetInserter()(SyncFIFO([("data", data_width)], fifo_depth))
 
             self.comb += [
                 fifo.reset.eq(self.reset),
diff --git a/litex/soc/cores/ram/xilinx_usp_hbm2.py b/litex/soc/cores/ram/xilinx_usp_hbm2.py
index b0ed356bd..270379917 100644
--- a/litex/soc/cores/ram/xilinx_usp_hbm2.py
+++ b/litex/soc/cores/ram/xilinx_usp_hbm2.py
@@ -19,7 +19,7 @@ from litex.soc.interconnect.csr import *
 
 # Ultrascale + HBM2 IP Wrapper ---------------------------------------------------------------------
 
-class USPHBM2(Module, AutoCSR):
+class USPHBM2(LiteXModule):
     """Xilinx Virtex US+ High Bandwidth Memory 2 IP wrapper"""
     def __init__(self, platform, hbm_ip_name="hbm_0"):
         self.platform = platform