diff --git a/litex/soc/cores/cpu/lm32/core.py b/litex/soc/cores/cpu/lm32/core.py
index 9f9072258..8e7eb1842 100644
--- a/litex/soc/cores/cpu/lm32/core.py
+++ b/litex/soc/cores/cpu/lm32/core.py
@@ -121,12 +121,13 @@ class LM32(CPU):
             "lm32_itlb.v",
             "lm32_dtlb.v")
         platform.add_verilog_include_path(os.path.join(vdir, "rtl"))
+        cdir = os.path.join(os.path.abspath(os.path.dirname(__file__)), "verilog")
         if variant == "minimal":
-            platform.add_verilog_include_path(os.path.join(vdir, "config_minimal"))
+            platform.add_verilog_include_path(os.path.join(cdir, "config_minimal"))
         elif variant == "lite":
-            platform.add_verilog_include_path(os.path.join(vdir, "config_lite"))
+            platform.add_verilog_include_path(os.path.join(cdir, "config_lite"))
         elif variant == "standard":
-            platform.add_verilog_include_path(os.path.join(vdir, "config"))
+            platform.add_verilog_include_path(os.path.join(cdir, "config"))
         else:
             raise TypeError("Unknown variant {}".format(variant))