diff --git a/litex/soc/cores/cpu/gowin_emcu/core.py b/litex/soc/cores/cpu/gowin_emcu/core.py
index 3c0352054..6d8f8da90 100644
--- a/litex/soc/cores/cpu/gowin_emcu/core.py
+++ b/litex/soc/cores/cpu/gowin_emcu/core.py
@@ -10,7 +10,8 @@ from migen import *
 from litex.gen import *
 
 from litex.soc.cores.cpu import CPU
-from litex.soc.interconnect import wishbone, ahb
+from litex.soc.interconnect import wishbone
+from litex.soc.interconnect import ahb
 
 # Gowin EMCU ---------------------------------------------------------------------------------------
 
@@ -160,7 +161,7 @@ class GowinEMCU(CPU):
                     i_NVSTR = 0
                 )
 
-        ahb_flash = ahb.Interface()
+        ahb_flash = ahb.AHBInterface()
         self.cpu_params.update(
             o_TARGFLASH0HADDR     = ahb_flash.addr,
             o_TARGFLASH0HBURST    = ahb_flash.burst,
@@ -178,7 +179,7 @@ class GowinEMCU(CPU):
 
         # Peripheral Bus (AHB -> Wishbone).
         # ---------------------------------
-        ahb_targexp0 = ahb.Interface()
+        ahb_targexp0 = ahb.AHBInterface()
         self.cpu_params.update(
             o_TARGEXP0HADDR     = ahb_targexp0.addr,
             o_TARGEXP0HBURST    = ahb_targexp0.burst,
diff --git a/litex/soc/interconnect/ahb.py b/litex/soc/interconnect/ahb.py
index e7c73f238..6d0943d0a 100644
--- a/litex/soc/interconnect/ahb.py
+++ b/litex/soc/interconnect/ahb.py
@@ -15,7 +15,7 @@ from litex.gen import *
 
 # Helpers ------------------------------------------------------------------------------------------
 
-class TransferType(IntEnum):
+class AHBTransferType(IntEnum):
     """Defines types of AHB transfers."""
     IDLE          = 0
     BUSY          = 1
@@ -24,7 +24,7 @@ class TransferType(IntEnum):
 
 # AHB Interface ------------------------------------------------------------------------------------
 
-class Interface(Record):
+class AHBInterface(Record):
     """Sets up the AHB interface signals for master and slave."""
     adr_width      = 32
     data_width     = 32
@@ -71,7 +71,7 @@ class AHB2Wishbone(LiteXModule):
             ahb.readyout.eq(1),
             If(ahb.sel &
               (ahb.size  <= log2_int(ahb.data_width//8)) &
-              (ahb.trans == TransferType.NONSEQUENTIAL),
+              (ahb.trans == AHBTransferType.NONSEQUENTIAL),
                NextValue(wishbone.adr,   ahb.addr[wishbone_adr_shift:]),
                NextValue(wishbone.dat_w, ahb.wdata),
                NextValue(wishbone.we,    ahb.write),