From 0392dd8ac2d495f2a9a11390a87668737ffc79da Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 6 Dec 2012 17:15:47 +0100 Subject: [PATCH] bank/csrgen: interface -> bus --- top.py | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/top.py b/top.py index 33708a9f6..419ee9d0f 100644 --- a/top.py +++ b/top.py @@ -114,13 +114,13 @@ def get(): fb0 = framebuffer.Framebuffer(csr_offset("FB"), asmiport_fb) asmiprobe0 = asmiprobe.ASMIprobe(csr_offset("ASMIPROBE"), asmicon0.hub) csrcon0 = csr.Interconnect(wishbone2csr0.csr, [ - uart0.bank.interface, - dfii0.bank.interface, - identifier0.bank.interface, - timer0.bank.interface, - minimac0.bank.interface, - fb0.bank.interface, - asmiprobe0.bank.interface + uart0.bank.bus, + dfii0.bank.bus, + identifier0.bank.bus, + timer0.bank.bus, + minimac0.bank.bus, + fb0.bank.bus, + asmiprobe0.bank.bus ]) #