From 03aa972bb66b161dc2080aa4826f3c31251405ee Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 8 Apr 2015 23:27:22 +0200 Subject: [PATCH] lite*: finish ModuleTransformer adaptations (need to be tested on board) --- misoclib/com/liteeth/generic/__init__.py | 8 ++++---- misoclib/mem/litesata/common.py | 8 ++++---- misoclib/mem/litesata/core/link/__init__.py | 4 ++-- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/misoclib/com/liteeth/generic/__init__.py b/misoclib/com/liteeth/generic/__init__.py index 053e50d72..d7049a996 100644 --- a/misoclib/com/liteeth/generic/__init__.py +++ b/misoclib/com/liteeth/generic/__init__.py @@ -29,15 +29,15 @@ class BufferizeEndpoints(ModuleTransformer): # add buffer on sinks for name, sink in sinks.items(): buf = Buffer(sink.description) - self.submodules += buf + submodule.submodules += buf setattr(self, name, buf.d) - self.comb += Record.connect(buf.q, sink) + submodule.comb += Record.connect(buf.q, sink) # add buffer on sources for name, source in sources.items(): buf = Buffer(source.description) - self.submodules += buf - self.comb += Record.connect(source, buf.d) + submodule.submodules += buf + submodule.comb += Record.connect(source, buf.d) setattr(self, name, buf.q) class EndpointPacketStatus(Module): diff --git a/misoclib/mem/litesata/common.py b/misoclib/mem/litesata/common.py index 2a3637756..0ccb8880e 100644 --- a/misoclib/mem/litesata/common.py +++ b/misoclib/mem/litesata/common.py @@ -270,15 +270,15 @@ class BufferizeEndpoints(ModuleTransformer): # add buffer on sinks for name, sink in sinks.items(): buf = Buffer(sink.description) - self.submodules += buf + submodule.submodules += buf setattr(self, name, buf.d) - self.comb += Record.connect(buf.q, sink) + submodule.comb += Record.connect(buf.q, sink) # add buffer on sources for name, source in sources.items(): buf = Buffer(source.description) - self.submodules += buf - self.comb += Record.connect(source, buf.d) + submodule.submodules += buf + submodule.comb += Record.connect(source, buf.d) setattr(self, name, buf.q) class EndpointPacketStatus(Module): diff --git a/misoclib/mem/litesata/core/link/__init__.py b/misoclib/mem/litesata/core/link/__init__.py index 74e3d611b..4c96398dd 100644 --- a/misoclib/mem/litesata/core/link/__init__.py +++ b/misoclib/mem/litesata/core/link/__init__.py @@ -35,7 +35,7 @@ class LiteSATALinkTX(Module): # inserter CONT and scrambled data between # CONT and next primitive - cont = BufferizeEndpoints(LiteSATACONTInserter(phy_description(32)), "source") + cont = BufferizeEndpoints("source")(LiteSATACONTInserter(phy_description(32))) self.submodules += cont # datas / primitives mux @@ -121,7 +121,7 @@ class LiteSATALinkRX(Module): self.submodules += fsm # CONT remover - cont = BufferizeEndpoints(LiteSATACONTRemover(phy_description(32)), "source") + cont = BufferizeEndpoints("source")(LiteSATACONTRemover(phy_description(32))) self.submodules += cont self.comb += Record.connect(phy.source, cont.sink)