From 041aa9bf6f2005ec98991d0330ee3e766a7a5be7 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 9 Feb 2021 19:06:49 +0100 Subject: [PATCH] soc/cores/clock/xilinx_us/USIDELAYCTRL: make sure sys clock domain is reseted when reference clock domain is reseted. --- litex/soc/cores/clock/xilinx_us.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/clock/xilinx_us.py b/litex/soc/cores/clock/xilinx_us.py index 2d4a93936..90a39c865 100644 --- a/litex/soc/cores/clock/xilinx_us.py +++ b/litex/soc/cores/clock/xilinx_us.py @@ -93,7 +93,6 @@ class USMMCM(XilinxClocking): class USIDELAYCTRL(Module): def __init__(self, cd_ref, cd_sys, reset_cycles=64, ready_cycles=64): - cd_sys.rst.reset = 1 self.clock_domains.cd_ic = ClockDomain() ic_reset_counter = Signal(max=reset_cycles, reset=reset_cycles-1) ic_reset = Signal(reset=1) @@ -109,6 +108,7 @@ class USIDELAYCTRL(Module): ic_ready = Signal() self.comb += self.cd_ic.clk.eq(cd_sys.clk) self.sync.ic += [ + cd_sys.rst.eq(1), If(ic_ready, If(ic_ready_counter != 0, ic_ready_counter.eq(ic_ready_counter - 1)