From 94ec68dd3cf809b729c7d1a872f350b97ca0e34b Mon Sep 17 00:00:00 2001 From: stone3311 Date: Tue, 3 Jan 2023 14:06:00 +0100 Subject: [PATCH 1/2] clock/intel: Add Stratix V PLL parameters --- litex/soc/cores/clock/intel_stratix5.py | 43 +++++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 litex/soc/cores/clock/intel_stratix5.py diff --git a/litex/soc/cores/clock/intel_stratix5.py b/litex/soc/cores/clock/intel_stratix5.py new file mode 100644 index 000000000..06793b31f --- /dev/null +++ b/litex/soc/cores/clock/intel_stratix5.py @@ -0,0 +1,43 @@ +# +# This file is part of LiteX. +# +# Copyright (c) 2018-2023 Florent Kermarrec +# SPDX-License-Identifier: BSD-2-Clause + +from migen import * + +from litex.soc.cores.clock.common import * +from litex.soc.cores.clock.intel_common import * + +# Intel / StratixV -------------------------------------------------------------------------------- + +class StratixVPLL(IntelClocking): + nclkouts_max = 18 + n_div_range = (1, 512+1) + m_div_range = (1, 512+1) + c_div_range = (1, 512+1) + clkin_pfd_freq_range = (5e6, 325e6) + def __init__(self, speedgrade="-C4"): + self.logger = logging.getLogger("StratixVPLL") + self.logger.info("Creating StratixVPLL, {}.".format(colorer("speedgrade {}".format(speedgrade)))) + IntelClocking.__init__(self) + + if speedgrade == "-C4" or speedgrade == "-I4": + self.clkin_freq_range = (5e6, 650e6) + self.vco_freq_range = (600e6, 1300e6) + else: + self.clkin_freq_range = (5e6, 800e6) + self.vco_freq_range = (600e6, 1600e6) + + self.clko_freq_range = { + "-C1" : (5e6, 717e6), + "-C2" : (5e6, 717e6), + "-C2L" : (5e6, 717e6), + "-I2" : (5e6, 717e6), + "-I2L" : (5e6, 717e6), + "-C3" : (5e6, 650e6), + "-I3" : (5e6, 650e6), + "-I3L" : (5e6, 650e6), + "-C4" : (5e6, 580e6), + "-I4" : (5e6, 580e6), + }[speedgrade] From 9443bfcd8f2ef428d01720e8b5c20c435dbe3d65 Mon Sep 17 00:00:00 2001 From: stone3311 Date: Thu, 5 Jan 2023 19:10:18 +0100 Subject: [PATCH 2/2] clock/intel: Edit copyright --- litex/soc/cores/clock/intel_stratix5.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/clock/intel_stratix5.py b/litex/soc/cores/clock/intel_stratix5.py index 06793b31f..0d3885c0b 100644 --- a/litex/soc/cores/clock/intel_stratix5.py +++ b/litex/soc/cores/clock/intel_stratix5.py @@ -1,7 +1,7 @@ # # This file is part of LiteX. # -# Copyright (c) 2018-2023 Florent Kermarrec +# Copyright (c) 2023 stone3311 # SPDX-License-Identifier: BSD-2-Clause from migen import *