From 0498a318182198bb2908dd183f32984dd8fdf684 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sun, 27 Dec 2015 12:01:29 +0100 Subject: [PATCH] some cleanup - remove Sink/Source connect specialization. - remove use of Record.connect - use sink/source on Buffer --- litex/soc/cores/sdram/phy/s6ddrphy.py | 8 ++-- litex/soc/cores/uart/core.py | 4 +- litex/soc/integration/soc_sdram.py | 6 +-- litex/soc/interconnect/stream.py | 52 +++++++++++-------------- litex/soc/interconnect/stream_packet.py | 12 +++--- litex/soc/interconnect/stream_sim.py | 2 +- litex/soc/interconnect/wishbone.py | 2 +- 7 files changed, 39 insertions(+), 47 deletions(-) diff --git a/litex/soc/cores/sdram/phy/s6ddrphy.py b/litex/soc/cores/sdram/phy/s6ddrphy.py index dfd3e0a2c..4678864da 100644 --- a/litex/soc/cores/sdram/phy/s6ddrphy.py +++ b/litex/soc/cores/sdram/phy/s6ddrphy.py @@ -453,11 +453,11 @@ class S6QuarterRateDDRPHY(Module): dfi_leave_out = set(["rddata", "rddata_valid", "wrdata_en"]) self.comb += [ If(~phase_sel, - Record.connect(self.dfi.phases[0], half_rate_phy.dfi.phases[0], leave_out=dfi_leave_out), - Record.connect(self.dfi.phases[1], half_rate_phy.dfi.phases[1], leave_out=dfi_leave_out), + self.dfi.phases[0].connect(half_rate_phy.dfi.phases[0], leave_out=dfi_leave_out), + self.dfi.phases[1].connect(half_rate_phy.dfi.phases[1], leave_out=dfi_leave_out), ).Else( - Record.connect(self.dfi.phases[2], half_rate_phy.dfi.phases[0], leave_out=dfi_leave_out), - Record.connect(self.dfi.phases[3], half_rate_phy.dfi.phases[1], leave_out=dfi_leave_out), + self.dfi.phases[2].connect(half_rate_phy.dfi.phases[0], leave_out=dfi_leave_out), + self.dfi.phases[3].connect(half_rate_phy.dfi.phases[1], leave_out=dfi_leave_out), ), ] wr_data_en = self.dfi.phases[self.settings.wrphase].wrdata_en & ~phase_sel diff --git a/litex/soc/cores/uart/core.py b/litex/soc/cores/uart/core.py index d394f5aa7..fba23dcd9 100644 --- a/litex/soc/cores/uart/core.py +++ b/litex/soc/cores/uart/core.py @@ -159,7 +159,7 @@ class UART(Module, AutoCSR): tx_fifo.sink.stb.eq(self._rxtx.re), tx_fifo.sink.data.eq(self._rxtx.r), self._txfull.status.eq(~tx_fifo.sink.ack), - Record.connect(tx_fifo.source, phy.sink), + tx_fifo.source.connect(phy.sink), # Generate TX IRQ when tx_fifo becomes non-full self.ev.tx.trigger.eq(~tx_fifo.sink.ack) ] @@ -169,7 +169,7 @@ class UART(Module, AutoCSR): self.submodules += rx_fifo self.comb += [ - Record.connect(phy.source, rx_fifo.sink), + phy.source.connect(rx_fifo.sink), self._rxempty.status.eq(~rx_fifo.source.stb), self._rxtx.w.eq(rx_fifo.source.data), rx_fifo.source.ack.eq(self.ev.rx.clear), diff --git a/litex/soc/integration/soc_sdram.py b/litex/soc/integration/soc_sdram.py index 3c3a3e836..c3f5678f1 100644 --- a/litex/soc/integration/soc_sdram.py +++ b/litex/soc/integration/soc_sdram.py @@ -14,13 +14,13 @@ class ControllerInjector(Module, AutoCSR): def __init__(self, phy, controller_type, geom_settings, timing_settings): self.submodules.dfii = dfii.DFIInjector(geom_settings.addressbits, geom_settings.bankbits, phy.settings.dfi_databits, phy.settings.nphases) - self.comb += Record.connect(self.dfii.master, phy.dfi) + self.comb += self.dfii.master.connect(phy.dfi) if controller_type == "lasmicon": self.submodules.controller = controller = lasmicon.LASMIcon(phy.settings, geom_settings, timing_settings) - self.comb += Record.connect(controller.dfi, self.dfii.slave) + self.comb += controller.dfi.connect(self.dfii.slave) self.submodules.crossbar = lasmi_bus.LASMIxbar([controller.lasmic], controller.nrowbits) @@ -28,7 +28,7 @@ class ControllerInjector(Module, AutoCSR): self.submodules.controller = controller = minicon.Minicon(phy.settings, geom_settings, timing_settings) - self.comb += Record.connect(controller.dfi, self.dfii.slave) + self.comb += controller.dfi.connect(self.dfii.slave) else: raise ValueError("Unsupported SDRAM controller type") diff --git a/litex/soc/interconnect/stream.py b/litex/soc/interconnect/stream.py index 9ddc5224e..59434a35c 100644 --- a/litex/soc/interconnect/stream.py +++ b/litex/soc/interconnect/stream.py @@ -59,13 +59,10 @@ class Endpoint(Record): class Source(Endpoint): - def connect(self, sink): - return Record.connect(self, sink) - + pass class Sink(Endpoint): - def connect(self, source): - return source.connect(self) + pass class _FIFOWrapper(Module): @@ -135,7 +132,7 @@ class Multiplexer(Module): cases = {} for i, sink in enumerate(sinks): - cases[i] = Record.connect(sink, self.source) + cases[i] = sink.connect(self.source) self.comb += Case(self.sel, cases) @@ -153,7 +150,7 @@ class Demultiplexer(Module): cases = {} for i, source in enumerate(sources): - cases[i] = Record.connect(self.sink, source) + cases[i] = self.sink.connect(source) self.comb += Case(self.sel, cases) # TODO: clean up code below @@ -254,13 +251,13 @@ class PipelinedActor(BinaryActor): class Buffer(PipelinedActor): def __init__(self, layout): - self.d = Sink(layout) - self.q = Source(layout) + self.sink = Sink(layout) + self.source = Source(layout) PipelinedActor.__init__(self, 1) self.sync += \ If(self.pipe_ce, - self.q.payload.eq(self.d.payload), - self.q.param.eq(self.d.param) + self.source.payload.eq(self.sink.payload), + self.source.param.eq(self.sink.param) ) @@ -428,7 +425,6 @@ class Converter(Module): def __init__(self, layout_from, layout_to, reverse=False): self.sink = Sink(layout_from) self.source = Source(layout_to) - self.busy = Signal() # # # @@ -443,12 +439,10 @@ class Converter(Module): self.submodules.chunkerize = Chunkerize(layout_from, layout_to, ratio, reverse) self.submodules.unpack = Unpack(ratio, layout_to) - self.comb += [ - Record.connect(self.sink, self.chunkerize.sink), - Record.connect(self.chunkerize.source, self.unpack.sink), - Record.connect(self.unpack.source, self.source), - self.busy.eq(self.unpack.busy) - ] + self.submodules += Pipeline(self.sink, + self.chunkerize, + self.unpack, + self.source) # upconverter elif width_to > width_from: if width_to % width_from: @@ -457,15 +451,13 @@ class Converter(Module): self.submodules.pack = Pack(layout_from, ratio) self.submodules.unchunkerize = Unchunkerize(layout_from, ratio, layout_to, reverse) - self.comb += [ - Record.connect(self.sink, self.pack.sink), - Record.connect(self.pack.source, self.unchunkerize.sink), - Record.connect(self.unchunkerize.source, self.source), - self.busy.eq(self.pack.busy) - ] + self.submodules += Pipeline(self.sink, + self.pack, + self.unchunkerize, + self.source) # direct connection else: - self.comb += Record.connect(self.sink, self.source) + self.comb += self.sink.connect(self.source) class Pipeline(Module): @@ -487,7 +479,7 @@ class Pipeline(Module): else: sink = m_n.sink if m is not m_n: - self.comb += Record.connect(source, sink) + self.comb += source.connect(sink) m = m_n # expose source of last module # if available @@ -515,14 +507,14 @@ class BufferizeEndpoints(ModuleTransformer): for name, sink in sinks.items(): buf = Buffer(sink.description) submodule.submodules += buf - setattr(submodule, name, buf.d) - submodule.comb += Record.connect(buf.q, sink) + setattr(submodule, name, buf.sink) + submodule.comb += buf.source.connect(sink) # add buffer on sources for name, source in sources.items(): buf = Buffer(source.description) submodule.submodules += buf - submodule.comb += Record.connect(source, buf.d) - setattr(submodule, name, buf.q) + submodule.comb += source.connect(buf.sink) + setattr(submodule, name, buf.source) # XXX diff --git a/litex/soc/interconnect/stream_packet.py b/litex/soc/interconnect/stream_packet.py index f892fedff..a051ac21c 100644 --- a/litex/soc/interconnect/stream_packet.py +++ b/litex/soc/interconnect/stream_packet.py @@ -38,7 +38,7 @@ class Arbiter(Module): pass elif len(masters) == 1: self.grant = Signal() - self.comb += Record.connect(masters.pop(), slave) + self.comb += masters.pop().connect(slave) else: self.submodules.rr = RoundRobin(len(masters)) self.grant = self.rr.grant @@ -47,7 +47,7 @@ class Arbiter(Module): status = Status(master) self.submodules += status self.comb += self.rr.request[i].eq(status.ongoing) - cases[i] = [Record.connect(master, slave)] + cases[i] = [master.connect(slave)] self.comb += Case(self.grant, cases) @@ -56,7 +56,7 @@ class Dispatcher(Module): if len(slaves) == 0: self.sel = Signal() elif len(slaves) == 1: - self.comb += Record.connect(master, slaves.pop()) + self.comb += master.connect(slaves.pop()) self.sel = Signal() else: if one_hot: @@ -87,7 +87,7 @@ class Dispatcher(Module): idx = 2**i else: idx = i - cases[idx] = [Record.connect(master, slave)] + cases[idx] = [master.connect(slave)] cases["default"] = [master.ack.eq(1)] self.comb += Case(sel, cases) @@ -350,7 +350,7 @@ class Buffer(Module): data_fifo = SyncFIFO(description, data_depth, buffered=True) self.submodules += data_fifo self.comb += [ - Record.connect(self.sink, data_fifo.sink), + self.sink.connect(data_fifo.sink, leave_out=set(["stb", "ack"])), data_fifo.sink.stb.eq(self.sink.stb & cmd_fifo.sink.ack), self.sink.ack.eq(data_fifo.sink.ack & cmd_fifo.sink.ack), ] @@ -376,7 +376,7 @@ class Buffer(Module): source_error = Signal() fsm.act("OUTPUT", - Record.connect(data_fifo.source, self.source), + data_fifo.source.connect(self.source, leave_out=set("error")), source_error.eq(cmd_fifo.source.error), If(source_status.eop, cmd_fifo.source.ack.eq(1), diff --git a/litex/soc/interconnect/stream_sim.py b/litex/soc/interconnect/stream_sim.py index ba345f64f..16b64163b 100644 --- a/litex/soc/interconnect/stream_sim.py +++ b/litex/soc/interconnect/stream_sim.py @@ -182,7 +182,7 @@ class AckRandomizer(Module): self.comb += \ If(self.run, - Record.connect(self.sink, self.source) + self.sink.connect(self.source) ).Else( self.source.stb.eq(0), self.sink.ack.eq(0), diff --git a/litex/soc/interconnect/wishbone.py b/litex/soc/interconnect/wishbone.py index c10cda4ee..48d002c40 100644 --- a/litex/soc/interconnect/wishbone.py +++ b/litex/soc/interconnect/wishbone.py @@ -445,7 +445,7 @@ class Converter(Module): upconverter = UpConverter(master, slave) self.submodules += upconverter else: - Record.connect(master, slave) + master.connect(slave) class Cache(Module):