From 04b8a912558033afc51dc673d85ade339c7d3786 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 10 Mar 2020 11:10:23 +0100 Subject: [PATCH] integration/soc: add FPGA device and System clock to logs. --- litex/soc/integration/soc.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 30f91f916..c8abc75af 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -661,6 +661,8 @@ class SoC(Module): self.logger.info(colorer("-"*80, color="bright")) self.logger.info(colorer("Creating SoC... ({})".format(build_time()))) self.logger.info(colorer("-"*80, color="bright")) + self.logger.info("FPGA device : {}.".format(platform.device)) + self.logger.info("System clock: {:3.2f}MHz.".format(sys_clk_freq/1e6)) # SoC attributes --------------------------------------------------------------------------- self.platform = platform