From 04c64eb1d88fb5a5ac8f2356fd7f901f4dd2865e Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 26 Jun 2015 00:20:58 +0200 Subject: [PATCH] litesata/example_designs: fix core generation (RAID introduced some changes on the PHY) --- .../example_designs/platforms/verilog_backend.py | 15 ++++++++------- .../mem/litesata/example_designs/targets/core.py | 6 +++++- misoclib/mem/litesata/phy/__init__.py | 1 + 3 files changed, 14 insertions(+), 8 deletions(-) diff --git a/misoclib/mem/litesata/example_designs/platforms/verilog_backend.py b/misoclib/mem/litesata/example_designs/platforms/verilog_backend.py index 3780b2da5..095913e42 100644 --- a/misoclib/mem/litesata/example_designs/platforms/verilog_backend.py +++ b/misoclib/mem/litesata/example_designs/platforms/verilog_backend.py @@ -4,14 +4,15 @@ from mibuild.xilinx.platform import XilinxPlatform _io = [ ("sys_clk", 0, Pins("X")), ("sys_rst", 1, Pins("X")), - + ("sata_clocks", 0, + Subsignal("refclk_p", Pins("X")), + Subsignal("refclk_n", Pins("X")), + ), ("sata", 0, - Subsignal("refclk_p", Pins("C8")), - Subsignal("refclk_n", Pins("C7")), - Subsignal("txp", Pins("D2")), - Subsignal("txn", Pins("D1")), - Subsignal("rxp", Pins("E4")), - Subsignal("rxn", Pins("E3")), + Subsignal("txp", Pins("X")), + Subsignal("txn", Pins("X")), + Subsignal("rxp", Pins("X")), + Subsignal("rxn", Pins("X")), ), ] diff --git a/misoclib/mem/litesata/example_designs/targets/core.py b/misoclib/mem/litesata/example_designs/targets/core.py index e15b259a8..9fbdc0537 100644 --- a/misoclib/mem/litesata/example_designs/targets/core.py +++ b/misoclib/mem/litesata/example_designs/targets/core.py @@ -17,7 +17,7 @@ class Core(Module): self.clk_freq = clk_freq # SATA PHY/Core/Frontend - self.submodules.sata_phy = LiteSATAPHY(platform.device, platform.request("sys_clk"), platform.request("sata"), "sata_gen2", clk_freq) + self.submodules.sata_phy = LiteSATAPHY(platform.device, platform.request("sata_clocks"), platform.request("sata"), "sata_gen2", clk_freq) self.submodules.sata_core = LiteSATACore(self.sata_phy) self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core) @@ -32,6 +32,10 @@ class Core(Module): ios = set() # Transceiver + for e in dir(self.sata_phy.clock_pads): + obj = getattr(self.sata_phy.clock_pads, e) + if isinstance(obj, Signal): + ios = ios.union({obj}) for e in dir(self.sata_phy.pads): obj = getattr(self.sata_phy.pads, e) if isinstance(obj, Signal): diff --git a/misoclib/mem/litesata/phy/__init__.py b/misoclib/mem/litesata/phy/__init__.py index 3f9b1a7cc..5df8c1116 100644 --- a/misoclib/mem/litesata/phy/__init__.py +++ b/misoclib/mem/litesata/phy/__init__.py @@ -5,6 +5,7 @@ from misoclib.mem.litesata.phy.datapath import * class LiteSATAPHY(Module): def __init__(self, device, clock_pads_or_refclk, pads, revision, clk_freq): + self.clock_pads = clock_pads_or_refclk self.pads = pads self.revision = revision