diff --git a/make.py b/make.py
index 84eebcbd7..f6f84f5c8 100644
--- a/make.py
+++ b/make.py
@@ -111,15 +111,14 @@ RLE: {}
 	str(soc.la.with_rle)
 	)
 )
+
 	# dependencies
 	if actions["all"]:
-		actions["clean"] = True
 		actions["build-csr-csv"] = True
 		actions["build-bitstream"] = True
 		actions["load-bitstream"] = True
 
 	if actions["build-bitstream"]:
-		actions["clean"] = True
 		actions["build-csr-csv"] = True
 		actions["build-bitstream"] = True
 		actions["load-bitstream"] = True
@@ -132,7 +131,10 @@ RLE: {}
 		write_to_file(args.csr_csv, csr_csv)
 
 	if actions["build-bitstream"]:
-		platform.build(soc, build_name=build_name)
+		vns = platform.build(soc, build_name=build_name)
+		if hasattr(soc, "do_exit") and vns is not None:
+			if hasattr(soc.do_exit, '__call__'):
+				soc.do_exit(vns)
 
 	if actions["load-bitstream"]:
 		prog = platform.create_programmer()
diff --git a/targets/simple.py b/targets/simple.py
index 9f9dca608..4f2f648cd 100644
--- a/targets/simple.py
+++ b/targets/simple.py
@@ -1,4 +1,4 @@
-import os, atexit
+import os
 
 from migen.bank import csrgen
 from migen.bus import wishbone, csr
@@ -99,10 +99,8 @@ class LiteScopeSoC(GenSoC, AutoCSR):
 		)
 		self.submodules.la = LiteScopeLA(self.debug, 512, with_subsampler=True)
 		self.la.trigger.add_port(LiteScopeTerm(self.la.dw))
-		atexit.register(self.exit, platform)
 
-	def exit(self, platform):
-		if platform.vns is not None:
-			self.la.export(platform.vns, "./test/la.csv")
+	def do_exit(self, vns):
+		self.la.export(vns, "test/la.csv")
 
 default_subtarget = LiteScopeSoC