From 053e540b8ae6ae4a5c8fdb2babf6b82f2bca373c Mon Sep 17 00:00:00 2001
From: Andrew Dennison <andrew@motec.com.au>
Date: Tue, 1 Jun 2021 09:49:58 +1000
Subject: [PATCH] soc/csr: ValueError if write would be truncated in simulation

---
 litex/soc/interconnect/csr.py | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/litex/soc/interconnect/csr.py b/litex/soc/interconnect/csr.py
index b9fc46e78..ab1730a0e 100644
--- a/litex/soc/interconnect/csr.py
+++ b/litex/soc/interconnect/csr.py
@@ -428,6 +428,8 @@ class CSRStorage(_CompoundCSR):
         """Write method for simulation.
 
         Side effects: synchronous advances simulation clk by one tick."""
+        if bits_for(value) > self.size:
+            raise ValueError(f"value {value} exceeds range of {self.size} bit CSR {self.name}.")
 
         yield self.storage.eq(value)
         yield self.re.eq(1)