diff --git a/litex/soc/cores/cpu/naxriscv/core.py b/litex/soc/cores/cpu/naxriscv/core.py
index acdbf5906..cc78bf90a 100644
--- a/litex/soc/cores/cpu/naxriscv/core.py
+++ b/litex/soc/cores/cpu/naxriscv/core.py
@@ -261,6 +261,9 @@ class NaxRiscv(CPU):
         soc.irq.add("uart",   n=0)
         soc.irq.add("timer0", n=1)
 
+        # Add OpenSBI region.
+        soc.add_memory_region("opensbi", self.mem_map["main_ram"] + 0x00f00000, 0x80000, type="cached+linker")
+
         # Define ISA.
         soc.add_constant("CPU_ISA", NaxRiscv.get_arch())
 
diff --git a/litex/soc/cores/cpu/vexriscv_smp/core.py b/litex/soc/cores/cpu/vexriscv_smp/core.py
index ee976d614..16210da7d 100755
--- a/litex/soc/cores/cpu/vexriscv_smp/core.py
+++ b/litex/soc/cores/cpu/vexriscv_smp/core.py
@@ -382,6 +382,9 @@ class VexRiscvSMP(CPU):
         soc.irq.add("uart",   n=0)
         soc.irq.add("timer0", n=1)
 
+        # Add OpenSBI region.
+        soc.add_memory_region("opensbi", self.mem_map["main_ram"] + 0x00f00000, 0x80000, type="cached+linker")
+
         # Define number of CPUs
         soc.add_config("CPU_COUNT", VexRiscvSMP.cpu_count)
         soc.add_constant("CPU_ISA", VexRiscvSMP.get_arch())