From 05724d9feace52a49ce4de9d2b791f61c353dff5 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 17 Mar 2022 16:28:25 +0100 Subject: [PATCH] cpu/naxriscv/vexriscv_smp: Declare/Add OpenSBI region in add_soc_compoents. Avoid doing it in Linux-on-LiteX-Vexriscv. --- litex/soc/cores/cpu/naxriscv/core.py | 3 +++ litex/soc/cores/cpu/vexriscv_smp/core.py | 3 +++ 2 files changed, 6 insertions(+) diff --git a/litex/soc/cores/cpu/naxriscv/core.py b/litex/soc/cores/cpu/naxriscv/core.py index acdbf5906..cc78bf90a 100644 --- a/litex/soc/cores/cpu/naxriscv/core.py +++ b/litex/soc/cores/cpu/naxriscv/core.py @@ -261,6 +261,9 @@ class NaxRiscv(CPU): soc.irq.add("uart", n=0) soc.irq.add("timer0", n=1) + # Add OpenSBI region. + soc.add_memory_region("opensbi", self.mem_map["main_ram"] + 0x00f00000, 0x80000, type="cached+linker") + # Define ISA. soc.add_constant("CPU_ISA", NaxRiscv.get_arch()) diff --git a/litex/soc/cores/cpu/vexriscv_smp/core.py b/litex/soc/cores/cpu/vexriscv_smp/core.py index ee976d614..16210da7d 100755 --- a/litex/soc/cores/cpu/vexriscv_smp/core.py +++ b/litex/soc/cores/cpu/vexriscv_smp/core.py @@ -382,6 +382,9 @@ class VexRiscvSMP(CPU): soc.irq.add("uart", n=0) soc.irq.add("timer0", n=1) + # Add OpenSBI region. + soc.add_memory_region("opensbi", self.mem_map["main_ram"] + 0x00f00000, 0x80000, type="cached+linker") + # Define number of CPUs soc.add_config("CPU_COUNT", VexRiscvSMP.cpu_count) soc.add_constant("CPU_ISA", VexRiscvSMP.get_arch())